91cd79a8a3
soc/runtime: add lwip (thanks Florent)
2015-04-17 14:51:30 +08:00
c1ece33e6d
manual: adapt to LED on RTIO
2015-04-17 10:43:50 +08:00
Yann Sionneau
52fe66ee4d
artiq_flash.sh: improve detection of flash proxy location
...
Flash proxy is now searched in ~/.migen /usr/local/share/migen
/usr/share/migen and in the directory specified by "-d" argument
or in artiq/binaries/<board_name>/ if "-d" is not specified.
2015-04-17 00:57:16 +08:00
6a5f58e5a9
runtime: support test mode on AMP
2015-04-16 21:47:05 +08:00
546996f896
coredevice,runtime: put ref_period into the ddb
2015-04-16 15:15:38 +08:00
485381fdbf
Merge branch 'master' of github.com:m-labs/artiq
2015-04-16 13:10:55 +08:00
71167b8adf
rtio: do not attempt latency compensation in gateware
2015-04-16 13:09:29 +08:00
6215d63491
rtio: do not create spurious CSRs when data_width/address_width is 0
2015-04-16 13:04:19 +08:00
26003781b4
rtio/rtlink: add 'like' methods to clone interfaces
2015-04-16 13:02:39 +08:00
a5ea40478c
runtime/Makefile: use printf instead of non-portable echo -e
2015-04-15 21:13:20 -06:00
61a6506484
targets/pipistrello: add mailbox memory region
2015-04-15 20:41:28 +08:00
Florent Kermarrec
fd2def4951
generate MAILBOX_BASE with SoC and use it in runtime
...
to avoid possible future mismatches between SoC/runtime, constants that can be easily generated from SoC should be defined this way.
2015-04-15 20:40:28 +08:00
30dffb6644
rtio/phy: add wishbone adapter
2015-04-15 20:39:40 +08:00
c1f9fc2ae4
runtime: update mailbox address
2015-04-15 14:11:12 +08:00
9cfe00e23e
runtime: keep .bin
2015-04-15 14:05:34 +08:00
ecf6b29279
coredevice/rtio: minor docstring cleanup
2015-04-15 13:53:00 +08:00
ffe4ee9137
runtime: build flash image by default
2015-04-15 12:43:15 +08:00
c0213c9f69
artiq_flash.sh: add pipistrello
2015-04-14 22:37:08 -06:00
d6f47b3bb0
benchmarks/examples: give comm_serial a device
...
These examples/benchmarks require manual handholding in
many cases anyway. Also, for comm_tcp manual changes are required.
Instead of nursing a bunch of different pdb and ddbs,
we probably want to force the user to copy and edit a template
that we then gitignore.
2015-04-14 21:50:40 -06:00
a336c95d0a
runtime/Makefile: work around echo vs bin/echo
2015-04-14 21:26:49 -06:00
f988ec318e
pipistrello: fix csrs, make AMP default
2015-04-14 21:10:07 -06:00
9795e83bfc
pdq2: continue work on coefficients
2015-04-14 18:18:49 -06:00
9e726d7dd1
ppro: ignore all async paths
2015-04-14 18:18:48 -06:00
70916aa0c5
pipistrello: tig _all_ async paths, add timing interference report
2015-04-14 18:18:48 -06:00
6a0e97f161
pdq2: refactor program_frame(), cleanup test, stall correctly
...
Once the Sequencer ack's a line, the Parser starts preparing the
next one. This includes jumping through the frame table if necessary.
To stall the Parser while the Sequencer executes the last line of a
frame and to ensure that the frame select lines can be set up and their
sampling is synchronized to a trigger, we add a triggered stall line
at the end of the frame.
When that line is triggered the Parser jumps through the table and starts
parsing the first line of the next frame. We let the duration of this
last stall line be 10 cycles (200ns@50MHz) to be able to distinguish this
sampling of the frame select lines from the triggering of the first line
in the next frame.
frame f
parser n f 0
stb __---________---___
trigger ___----_______----_
ack ____-__________-___
sequencer n-1 n 0
2015-04-14 18:18:16 -06:00
bc1acef355
test/pdq2: don't write vcd
2015-04-14 18:18:16 -06:00
066adbdeac
pipistrello: timing report
2015-04-14 18:18:16 -06:00
6217cf5392
pipistrello: basesoc, cleanup
2015-04-14 18:18:16 -06:00
4c10182c9f
rtio: refactor, use rtlink
2015-04-14 19:44:45 +08:00
c0f1708c20
targets/pipstrello: fix mem_map
2015-04-14 19:34:14 +08:00
ff9a7727d2
rtio: add rtlink definition (currently unused)
2015-04-13 22:19:18 +08:00
07b8e1292f
artiq_flash: fix stderr redirections
2015-04-11 23:43:33 +08:00
8a2b8fc634
artiq_flash: do not always assume permission problems
2015-04-11 22:54:17 +08:00
Yann Sionneau
8a3be4eca0
artiq_flash: add support for kc705
2015-04-11 22:38:11 +08:00
a50f2c20ff
targets/ppro: fix mem_map update
2015-04-11 21:59:29 +08:00
601f593ac4
targets/kc705: do not depend on particular Migen generated signal names
2015-04-11 21:46:57 +08:00
Florent Kermarrec
bdd02a064e
targets/artiq_kc705: add false path between rsys_clk and rio_clk (reduce P&R on AMP from 40 minutes to 5 minutes :)
2015-04-11 21:32:46 +08:00
Florent Kermarrec
24b2bd7b6f
soc/targets: use mem_map, fix addressing conflict on UP between ethernet and dds
2015-04-11 21:32:11 +08:00
fb75bd246e
targets/kc705: make AMP the default
2015-04-11 17:16:25 +08:00
b492aad1c4
targets/kc705: enable Ethernet core
2015-04-10 13:15:32 +08:00
88e0aae16d
coredevice: add comm_tcp
2015-04-10 01:22:03 +08:00
f427041ae9
coredevice/comm_serial: minor cleanup
2015-04-10 01:21:47 +08:00
cb2596bd81
coredevice/comm: split protocol to allow reuse for Ethernet
2015-04-10 00:59:35 +08:00
44304a33b2
soc,runtime: define RTIO FUD channel number in targets
2015-04-09 00:35:11 +08:00
efd1c24ed7
frontend: add artiq_compile tool to build default experiment
2015-04-07 15:41:32 +08:00
ca89b6d0ed
worker_db: support read-only mode
2015-04-07 15:40:57 +08:00
fda4ee1a83
coredevice: add compile method
2015-04-07 15:40:25 +08:00
5e046dc5ce
artiq_run: move parse_arguments and get_experiment to tools
2015-04-07 13:04:47 +08:00
2456e795dd
conda: add missing entry_points
2015-04-07 11:17:47 +08:00
1ddcfc13fb
conda: fix bitstream name
2015-04-07 11:17:25 +08:00
