forked from M-Labs/artiq
rtio: do not attempt latency compensation in gateware
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parent
6215d63491
commit
71167b8adf
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@ -318,9 +318,6 @@ class RTIO(Module):
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self.specials += AsyncResetSynchronizer(self.cd_rio,
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self.kcsrs.reset.storage)
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# Latency compensation
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# TODO
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# Managers
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self.submodules.counter = _RTIOCounter(counter_width)
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@ -4,17 +4,15 @@ from artiq.gateware.rtio import rtlink
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class RT2WB(Module):
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def __init__(self, wb, address_width, o_latency=0, i_latency=0):
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def __init__(self, wb, address_width):
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self.rtlink = rtlink.Interface(
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rtlink.OInterface(
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flen(wb.dat_w),
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address_width + 1,
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latency=o_latency,
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suppress_nop=False),
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rtlink.IInterface(
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flen(wb.dat_r),
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timestamped=False,
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latency=i_latency)
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timestamped=False)
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)
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# # #
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@ -3,7 +3,7 @@ from migen.fhdl.std import *
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class OInterface:
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def __init__(self, data_width, address_width=0,
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fine_ts_width=0, latency=1, suppress_nop=True):
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fine_ts_width=0, suppress_nop=True):
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self.stb = Signal()
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self.busy = Signal()
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@ -14,7 +14,6 @@ class OInterface:
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if fine_ts_width:
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self.fine_ts = Signal(fine_ts_width)
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self.latency = latency
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self.suppress_nop = suppress_nop
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@classmethod
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@ -22,12 +21,12 @@ class OInterface:
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return cls(get_data_width(other),
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get_address_width(other),
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get_fine_ts_width(other),
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other.latency, other.suppress_nop)
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other.suppress_nop)
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class IInterface:
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def __init__(self, data_width,
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timestamped=True, fine_ts_width=0, latency=2):
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timestamped=True, fine_ts_width=0):
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self.stb = Signal()
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if data_width:
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@ -35,7 +34,6 @@ class IInterface:
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if fine_ts_width:
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self.fine_ts = Signal(fine_ts_width)
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self.latency = latency
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self.timestamped = timestamped
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assert(not fine_ts_width or timestamped)
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@ -43,8 +41,7 @@ class IInterface:
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def like(cls, other):
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return cls(get_data_width(other),
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other.timestamped,
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get_fine_ts_width(other),
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other.latency)
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get_fine_ts_width(other))
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class Interface:
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