forked from M-Labs/artiq
rtio: do not create spurious CSRs when data_width/address_width is 0
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26003781b4
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6215d63491
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@ -268,15 +268,18 @@ class _KernelCSRs(AutoCSR):
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self.reset = CSRStorage(reset=1)
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self.chan_sel = CSRStorage(chan_sel_width)
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self.o_data = CSRStorage(data_width)
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self.o_address = CSRStorage(address_width)
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if data_width:
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self.o_data = CSRStorage(data_width)
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if address_width:
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self.o_address = CSRStorage(address_width)
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self.o_timestamp = CSRStorage(full_ts_width)
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self.o_we = CSR()
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self.o_status = CSRStatus(3)
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self.o_underflow_reset = CSR()
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self.o_sequence_error_reset = CSR()
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self.i_data = CSRStatus(data_width)
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if data_width:
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self.i_data = CSRStatus(data_width)
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self.i_timestamp = CSRStatus(full_ts_width)
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self.i_re = CSR()
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self.i_status = CSRStatus(2)
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@ -299,8 +302,7 @@ class RTIO(Module):
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# CSRs
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self.csrs = _CSRs()
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self.kcsrs = _KernelCSRs(bits_for(len(channels)-1),
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max(data_width, 1),
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max(address_width, 1),
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data_width, address_width,
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counter_width + fine_ts_width)
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# Clocking/Reset
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@ -391,8 +393,9 @@ class RTIO(Module):
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i_datas.append(0)
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i_timestamps.append(0)
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i_statuses.append(0)
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if data_width:
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self.comb += self.kcsrs.i_data.status.eq(Array(i_datas)[sel])
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self.comb += [
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self.kcsrs.i_data.status.eq(Array(i_datas)[sel]),
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self.kcsrs.i_timestamp.status.eq(Array(i_timestamps)[sel]),
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self.kcsrs.o_status.status.eq(Array(o_statuses)[sel]),
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self.kcsrs.i_status.status.eq(Array(i_statuses)[sel])
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