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da917f768e
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initial kc705 support
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2015-02-26 21:50:52 -07:00 |
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c591f1a74d
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targets/ARTIQMiniSoC: support dynamic switching of RTIO clock to XTRIG
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2014-12-01 18:53:29 +08:00 |
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99d530e498
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targets/ARTIQMiniSoC: remove 2 TTL channels to make room in FPGA
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2014-12-01 17:31:35 +08:00 |
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7166ca82d1
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targets/ARTIQMiniSoC: map RTIO CSRs directly on Wishbone (reduces programming time by 30%)
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2014-11-30 22:31:55 +08:00 |
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1f6441948d
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more TTL channels and larger input FIFOs on Papilio Pro
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2014-11-30 15:50:57 +08:00 |
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39c4b5416f
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targets/ARTIQMiniSoC: 125MHz RTIO clocking
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2014-11-30 01:00:27 +08:00 |
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901073acf3
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asynchronous RTIO
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2014-11-30 00:13:54 +08:00 |
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44ec3eae3d
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soc/target: use minicon by default
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2014-11-28 10:21:43 +08:00 |
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65567e1201
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soc/target: remap RTIO to avoid conflict with Ethernet MAC+PHY
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2014-11-21 15:51:51 -08:00 |
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346cca9e90
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soc/target: remap RTIO to avoid conflict with spiflash and ddrphy in MiSoC
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2014-10-21 18:40:08 +08:00 |
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af0cd902d3
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get frequency from RTIO, support fractional frequencies
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2014-09-26 17:24:06 +08:00 |
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f0f65ba3a7
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soc/target: add optional test signal generator
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2014-09-17 19:53:55 +08:00 |
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2c0b6ff4cc
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soc/target: connect FUD to RTIO
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2014-09-11 23:11:22 +08:00 |
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8d7591dfcf
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more PEP8
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2014-09-05 17:06:41 +08:00 |
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4915b4b5aa
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PEP8
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2014-09-05 12:03:22 +08:00 |
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1ed808e848
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soc/target: share base PPro design with MiSoC
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2014-08-03 12:26:15 +08:00 |
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f03ae5e5b0
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soc/rtio: separate PHY, add OE and fine timestamp in FIFO
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2014-07-24 23:50:20 -06:00 |
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005d66c7cd
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soc/dds: fix timing
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2014-07-22 17:44:41 -06:00 |
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2358b218bf
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soc: add DDS interface core
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2014-07-22 11:37:53 -06:00 |
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5573cf3688
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soc: add tester IO
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2014-07-22 10:45:59 -06:00 |
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ede3667fd3
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soc/target: use only 8 TTL channels for now
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2014-07-20 18:38:41 -06:00 |
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3b4bb41a19
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add basic output-only untested RTIO core
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2014-07-16 19:13:11 -06:00 |
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d804f1199e
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soc: add LED
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2014-07-05 22:44:20 +02:00 |
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6072f0c42f
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Basic SoC and runtime design
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2014-07-04 17:49:08 +02:00 |
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