forked from M-Labs/artiq
soc/rtio: separate PHY, add OE and fine timestamp in FIFO
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@ -3,10 +3,14 @@ from migen.bank.description import *
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from migen.genlib.fifo import SyncFIFOBuffered
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from migen.genlib.cdc import MultiReg
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from types import SimpleNamespace
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from artiqlib.rtio import phy
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class RTIOBankO(Module):
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def __init__(self, channels, counter_width, fifo_depth):
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def __init__(self, channels, counter_width, fine_ts_width, fifo_depth):
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self.sel = Signal(max=len(channels))
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self.timestamp = Signal(counter_width)
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self.timestamp = Signal(counter_width+fine_ts_width)
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self.value = Signal()
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self.writable = Signal()
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self.we = Signal()
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@ -19,14 +23,14 @@ class RTIOBankO(Module):
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self.sync += [
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counter.eq(counter + 1),
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If(self.we & self.writable,
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If(self.timestamp < counter + 2, self.underflow.eq(1))
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If(self.timestamp[fine_ts_width:] < counter + 2, self.underflow.eq(1))
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)
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]
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fifos = []
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for n, channel in enumerate(channels):
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fifo = SyncFIFOBuffered([
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("timestamp", counter_width), ("value", 1)],
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("timestamp", counter_width+fine_ts_width), ("value", 2)],
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fifo_depth)
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self.submodules += fifo
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fifos.append(fifo)
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@ -39,30 +43,50 @@ class RTIOBankO(Module):
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]
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# FIFO read
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time_hit = Signal()
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self.comb += [
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time_hit.eq(fifo.readable &
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(fifo.dout.timestamp == counter)),
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fifo.re.eq(time_hit)
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channel.hit.eq(fifo.readable &
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(fifo.dout.timestamp[fine_ts_width:] == counter)),
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channel.value.eq(fifo.dout.value),
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fifo.re.eq(channel.hit)
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]
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self.sync += If(time_hit, channel.eq(fifo.dout.value))
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if fine_ts_width:
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self.comb += channel.fine_ts.eq(fifo.dout.timestamp[:fine_ts_width])
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selfifo = Array(fifos)[self.sel]
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self.comb += self.writable.eq(selfifo.writable), self.level.eq(selfifo.level)
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class RTIO(Module, AutoCSR):
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def __init__(self, channels, counter_width=32, ofifo_depth=8, ififo_depth=8):
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self.submodules.bank_o = InsertReset(RTIOBankO(channels, counter_width, ofifo_depth))
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def __init__(self, phy, counter_width=32, ofifo_depth=8, ififo_depth=8):
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# Extract info from PHY
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if hasattr(phy.interface[0], "o_fine_ts"):
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fine_ts_width = flen(channels[0].o_fine_ts)
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else:
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fine_ts_width = 0
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oes = [padif.oe for padif in phy.interface if hasattr(padif, "oe")]
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# Submodules
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self.submodules.bank_o = InsertReset(RTIOBankO(
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[SimpleNamespace(hit=padif.o_set_value,
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value=padif.o_value,
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fine_ts=getattr(padif, "o_fine_ts", None))
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for padif in phy.interface],
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counter_width, fine_ts_width, ofifo_depth))
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# CSRs
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self._r_reset = CSRStorage(reset=1)
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self._r_oe = CSRStorage(len(oes))
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self._r_chan_sel = CSRStorage(flen(self.bank_o.sel))
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self._r_o_timestamp = CSRStorage(counter_width)
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self._r_o_timestamp = CSRStorage(counter_width+fine_ts_width)
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self._r_o_value = CSRStorage()
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self._r_o_writable = CSRStatus()
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self._r_o_we = CSR()
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self._r_o_underflow = CSRStatus()
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self._r_o_level = CSRStatus(bits_for(ofifo_depth))
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# OE
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self.comb += Cat(*oes).eq(self._r_oe.storage)
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# Output/Gate
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self.comb += [
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self.bank_o.reset.eq(self._r_reset.storage),
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self.bank_o.sel.eq(self._r_chan_sel.storage),
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@ -0,0 +1,50 @@
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from migen.fhdl.std import *
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from migen.genlib.cdc import MultiReg
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from migen.genlib.record import Record
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class PHYBase(Module):
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def __init__(self, fine_ts_bits, pads, output_only_pads):
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self.interface = []
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for pad in pads:
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layout = [
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("o_set_value", 1),
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("o_value", 1)
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]
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if fine_ts_bits:
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layout.append(("o_fine_ts", fine_ts_bits))
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if pad not in output_only_pads:
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layout += [
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("oe", 1),
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("i_detect", 1),
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("i_value", 1)
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]
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if fine_ts_bits:
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layout.append(("i_fine_ts", fine_ts_bits))
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self.interface.append(Record(layout))
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class SimplePHY(PHYBase):
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def __init__(self, pads, output_only_pads=set()):
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PHYBase.__init__(self, 0, pads, output_only_pads)
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for pad, padif in zip(pads, self.interface):
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o_pad_d1 = Signal()
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o_pad = Signal()
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self.sync += [
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If(padif.o_set_value, o_pad_d1.eq(padif.o_value)),
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o_pad.eq(o_pad_d1)
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]
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if pad in output_only_pads:
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self.comb += pad.eq(o_pad)
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else:
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ts = TSTriple()
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i_pad = Signal()
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self.sync += ts.oe.eq(padif.oe)
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self.comb += ts.o.eq(o_pad)
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self.specials += MultiReg(ts.i, i_pad), \
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ts.get_tristate(pad)
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i_pad_d = Signal()
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self.sync += i_pad_d.eq(i_pad)
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self.comb += padif.i_detect.eq(i_pad ^ i_pad_d), \
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padif.i_value.eq(i_pad)
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@ -122,8 +122,13 @@ class ARTIQSoC(SDRAMSoC):
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self.submodules.leds = gpio.GPIOOut(Cat(platform.request("user_led", 0),
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platform.request("user_led", 1)))
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self.comb += platform.request("ttl_tx_en").eq(1)
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self.submodules.rtio = rtio.RTIO([platform.request("ttl", i) for i in range(4)])
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rtio_pads = [platform.request("ttl", i) for i in range(4)]
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self.submodules.rtiophy = rtio.phy.SimplePHY(rtio_pads,
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{rtio_pads[1], rtio_pads[2], rtio_pads[3]})
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self.submodules.rtio = rtio.RTIO(self.rtiophy)
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self.submodules.dds = ad9858.AD9858(platform.request("dds"))
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self.add_wb_slave(lambda a: a[26:29] == 3, self.dds.bus)
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