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soc/target: add optional test signal generator

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This commit is contained in:
Sebastien Bourdeauducq 2014-09-17 19:53:55 +08:00
parent 9b8a91e67e
commit f0f65ba3a7
1 changed files with 16 additions and 1 deletions
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17
soc/targets/artiq.py
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@ -13,6 +13,7 @@ _tester_io = [
("ttl", 1, Pins("C:11"), IOStandard("LVTTL")),
("ttl", 2, Pins("C:10"), IOStandard("LVTTL")),
("ttl", 3, Pins("C:9"), IOStandard("LVTTL")),
("ttl", 4, Pins("C:8"), IOStandard("LVTTL")),
("ttl_tx_en", 0, Pins("A:9"), IOStandard("LVTTL")),
("dds", 0,
Subsignal("a", Pins("A:5 B:10 A:6 B:9 A:7 B:8")),
@ -27,13 +28,24 @@ _tester_io = [
]
class _TestGen(Module):
def __init__(self, pad):
divc = Signal(15)
ce = Signal()
self.sync += Cat(divc, ce).eq(divc + 1)
sr = Signal(8, reset=0b10101000)
self.sync += If(ce, sr.eq(Cat(sr[1:], sr[0])))
self.comb += pad.eq(sr[0])
class ARTIQMiniSoC(BaseSoC):
csr_map = {
"rtio": 10
}
csr_map.update(BaseSoC.csr_map)
def __init__(self, platform, cpu_type="or1k", **kwargs):
def __init__(self, platform, cpu_type="or1k", with_test_gen=False, **kwargs):
BaseSoC.__init__(self, platform, cpu_type=cpu_type, **kwargs)
platform.add_extension(_tester_io)
@ -51,6 +63,9 @@ class ARTIQMiniSoC(BaseSoC):
mini_pads={fud})
self.submodules.rtio = rtio.RTIO(self.rtiophy)
if with_test_gen:
self.submodules.test_gen = _TestGen(platform.request("ttl", 4))
dds_pads = platform.request("dds")
self.submodules.dds = ad9858.AD9858(dds_pads)
self.add_wb_slave(lambda a: a[26:29] == 3, self.dds.bus)