forked from M-Labs/artiq
soc: add tester IO
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8769066e89
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5573cf3688
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@ -121,7 +121,13 @@ static int rpc(int rpc_num, int n_args, ...)
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static void gpio_set(int channel, int value)
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{
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leds_out_write(value);
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static int csr_value;
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if(value)
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csr_value |= 1 << channel;
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else
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csr_value &= ~(1 << channel);
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leds_out_write(csr_value);
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}
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static void rtio_set(int timestamp, int channel, int value)
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@ -60,7 +60,24 @@ class _CRG(Module):
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i_C0=self.cd_sys.clk, i_C1=~self.cd_sys.clk,
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o_Q=platform.request("sdram_clock"))
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_ttl_io = [("ttl", i, Pins("C:"+str(i)), IOStandard("LVTTL")) for i in range(16)]
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_tester_io = [
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("user_led", 1, Pins("B:7"), IOStandard("LVTTL")),
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("ttl", 0, Pins("C:13"), IOStandard("LVTTL")),
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("ttl", 1, Pins("C:11"), IOStandard("LVTTL")),
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("ttl", 2, Pins("C:10"), IOStandard("LVTTL")),
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("ttl", 3, Pins("C:9"), IOStandard("LVTTL")),
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("ttl_tx_en", 0, Pins("A:9"), IOStandard("LVTTL")),
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("dds", 0,
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Subsignal("a", Pins("A:5 B:10 A:6 B:9 A:7 B:8")),
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Subsignal("d", Pins("A:12 B:3 A:13 B:2 A:14 B:1 A:15 B:0")),
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Subsignal("sel", Pins("A:2 B:14 A:1 B:15 A:0")),
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Subsignal("p", Pins("A:8 B:12")),
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Subsignal("fud", Pins("B:11")),
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Subsignal("wr_n", Pins("A:4")),
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Subsignal("rd_n", Pins("B:13")),
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Subsignal("reset", Pins("A:3")),
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IOStandard("LVTTL")),
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]
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class ARTIQSoC(SDRAMSoC):
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default_platform = "papilio_pro"
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@ -74,7 +91,7 @@ class ARTIQSoC(SDRAMSoC):
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clk_freq = 80*1000*1000
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SDRAMSoC.__init__(self, platform, clk_freq,
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cpu_reset_address=0x160000, cpu_type=cpu_type, **kwargs)
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platform.add_extension(_ttl_io)
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platform.add_extension(_tester_io)
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self.submodules.crg = _CRG(platform, clk_freq)
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@ -103,7 +120,9 @@ class ARTIQSoC(SDRAMSoC):
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self.flash_boot_address = 0x70000
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self.register_rom(self.spiflash.bus)
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self.submodules.leds = gpio.GPIOOut(platform.request("user_led"))
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self.submodules.rtio = rtio.RTIO([platform.request("ttl", i) for i in range(8)])
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self.submodules.leds = gpio.GPIOOut(Cat(platform.request("user_led", 0),
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platform.request("user_led", 1)))
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self.comb += platform.request("ttl_tx_en").eq(1)
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self.submodules.rtio = rtio.RTIO([platform.request("ttl", i) for i in range(4)])
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default_subtarget = ARTIQSoC
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