forked from M-Labs/artiq
more PEP8
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86193437f5
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@ -12,7 +12,7 @@ class AD9858(Module):
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Data is zero-padded.
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Write to address 64 to pulse the FUD signal.
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Address 65 is a GPIO register that controls the sel, p and reset signals.
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Address 65 is a GPIO register that controls the sel, p and reset signals.
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sel is mapped to the lower bits, followed by p and reset.
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Write timing:
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@ -55,9 +55,9 @@ class AD9858(Module):
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gpio_load = Signal()
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self.sync += If(gpio_load, gpio.eq(bus.dat_w))
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self.comb += [
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Cat(pads.sel, pads.p).eq(gpio),
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pads.rst_n.eq(~gpio[-1]),
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]
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Cat(pads.sel, pads.p).eq(gpio),
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pads.rst_n.eq(~gpio[-1]),
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]
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bus_r_gpio = Signal()
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self.comb += If(bus_r_gpio,
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@ -193,7 +193,8 @@ class _TB(Module):
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pads = _TestPads()
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self.submodules.dut = AD9858(pads)
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self.submodules.initiator = wishbone.Initiator(_test_gen())
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self.submodules.interconnect = wishbone.InterconnectPointToPoint(self.initiator.bus, self.dut.bus)
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self.submodules.interconnect = wishbone.InterconnectPointToPoint(
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self.initiator.bus, self.dut.bus)
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if __name__ == "__main__":
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@ -1,13 +1,13 @@
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from migen.fhdl.std import *
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from migen.bank.description import *
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from migen.genlib.fifo import SyncFIFOBuffered
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from migen.genlib.cdc import MultiReg
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from artiqlib.rtio.rbus import get_fine_ts_width
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class _RTIOBankO(Module):
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def __init__(self, rbus, counter_width, fine_ts_width, fifo_depth, counter_init):
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def __init__(self, rbus, counter_width, fine_ts_width,
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fifo_depth, counter_init):
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self.sel = Signal(max=len(rbus))
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self.timestamp = Signal(counter_width+fine_ts_width)
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self.value = Signal(2)
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@ -22,7 +22,8 @@ class _RTIOBankO(Module):
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self.sync += [
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counter.eq(counter + 1),
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If(self.we & self.writable,
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If(self.timestamp[fine_ts_width:] < counter + 2, self.underflow.eq(1))
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If(self.timestamp[fine_ts_width:] < counter + 2,
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self.underflow.eq(1))
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)
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]
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@ -49,10 +50,14 @@ class _RTIOBankO(Module):
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fifo.re.eq(chif.o_stb)
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]
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if fine_ts_width:
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self.comb += chif.o_fine_ts.eq(fifo.dout.timestamp[:fine_ts_width])
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self.comb += chif.o_fine_ts.eq(
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fifo.dout.timestamp[:fine_ts_width])
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selfifo = Array(fifos)[self.sel]
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self.comb += self.writable.eq(selfifo.writable), self.level.eq(selfifo.level)
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self.comb += [
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self.writable.eq(selfifo.writable),
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self.level.eq(selfifo.level)
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]
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class _RTIOBankI(Module):
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@ -83,7 +88,7 @@ class _RTIOBankI(Module):
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("timestamp", counter_width+fine_ts_width), ("value", 1)],
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fifo_depth)
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self.submodules += fifo
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# FIFO write
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if fine_ts_width:
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full_ts = Cat(chif.i_fine_ts, counter)
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@ -92,8 +97,10 @@ class _RTIOBankI(Module):
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self.comb += [
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fifo.din.timestamp.eq(full_ts),
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fifo.din.value.eq(chif.i_value),
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fifo.we.eq(~chif.oe & chif.i_stb &
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((chif.i_value & sensitivity[0]) | (~chif.i_value & sensitivity[1])))
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fifo.we.eq(
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~chif.oe & chif.i_stb &
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((chif.i_value & sensitivity[0])
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| (~chif.i_value & sensitivity[1])))
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]
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# FIFO read
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@ -101,7 +108,7 @@ class _RTIOBankI(Module):
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values.append(fifo.dout.value)
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readables.append(fifo.readable)
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self.comb += fifo.re.eq(self.re & (self.sel == n))
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overflow = Signal()
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self.sync += If(fifo.we & ~fifo.writable, overflow.eq(1))
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overflows.append(overflow)
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@ -124,16 +131,18 @@ class RTIO(Module, AutoCSR):
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fine_ts_width = get_fine_ts_width(phy.rbus)
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# Submodules
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self.submodules.bank_o = InsertReset(_RTIOBankO(phy.rbus,
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self.submodules.bank_o = InsertReset(_RTIOBankO(
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phy.rbus,
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counter_width, fine_ts_width, ofifo_depth,
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phy.loopback_latency))
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self.submodules.bank_i = InsertReset(_RTIOBankI(phy.rbus,
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self.submodules.bank_i = InsertReset(_RTIOBankI(
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phy.rbus,
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counter_width, fine_ts_width, ofifo_depth))
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# CSRs
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self._r_reset = CSRStorage(reset=1)
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self._r_chan_sel = CSRStorage(flen(self.bank_o.sel))
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self._r_oe = CSR()
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self._r_o_timestamp = CSRStorage(counter_width+fine_ts_width)
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@ -1,6 +1,7 @@
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from migen.fhdl.std import *
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from migen.genlib.record import Record
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def create_rbus(fine_ts_bits, pads, output_only_pads):
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rbus = []
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for pad in pads:
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@ -21,6 +22,7 @@ def create_rbus(fine_ts_bits, pads, output_only_pads):
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rbus.append(Record(layout))
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return rbus
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def get_fine_ts_width(rbus):
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if hasattr(rbus[0], "o_fine_ts"):
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return flen(rbus[0].o_fine_ts)
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@ -6,6 +6,7 @@ from targets.ppro import BaseSoC
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from artiqlib import rtio, ad9858
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_tester_io = [
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("user_led", 1, Pins("B:7"), IOStandard("LVTTL")),
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("ttl", 0, Pins("C:13"), IOStandard("LVTTL")),
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@ -25,6 +26,7 @@ _tester_io = [
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IOStandard("LVTTL")),
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]
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class ARTIQMiniSoC(BaseSoC):
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csr_map = {
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"rtio": 10
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@ -35,12 +37,14 @@ class ARTIQMiniSoC(BaseSoC):
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BaseSoC.__init__(self, platform, cpu_type=cpu_type, **kwargs)
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platform.add_extension(_tester_io)
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self.submodules.leds = gpio.GPIOOut(Cat(platform.request("user_led", 0),
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self.submodules.leds = gpio.GPIOOut(Cat(
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platform.request("user_led", 0),
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platform.request("user_led", 1)))
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self.comb += platform.request("ttl_tx_en").eq(1)
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rtio_pads = [platform.request("ttl", i) for i in range(4)]
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self.submodules.rtiophy = rtio.phy.SimplePHY(rtio_pads,
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self.submodules.rtiophy = rtio.phy.SimplePHY(
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rtio_pads,
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{rtio_pads[1], rtio_pads[2], rtio_pads[3]})
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self.submodules.rtio = rtio.RTIO(self.rtiophy)
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