forked from M-Labs/artiq
soc/target: use only 8 TTL channels for now
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@ -104,6 +104,6 @@ class ARTIQSoC(SDRAMSoC):
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self.register_rom(self.spiflash.bus)
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self.submodules.leds = gpio.GPIOOut(platform.request("user_led"))
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self.submodules.rtio = rtio.RTIO([platform.request("ttl", i) for i in range(16)])
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self.submodules.rtio = rtio.RTIO([platform.request("ttl", i) for i in range(8)])
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default_subtarget = ARTIQSoC
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