forked from M-Labs/artiq
soc/target: remap RTIO to avoid conflict with Ethernet MAC+PHY
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@ -41,7 +41,7 @@ class _TestGen(Module):
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class ARTIQMiniSoC(BaseSoC):
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csr_map = {
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"rtio": 12
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"rtio": 13
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}
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csr_map.update(BaseSoC.csr_map)
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