srenblad/artiq
1
0
Fork 0
forked from M-Labs/artiq
Code Pull Requests Activity

soc/target: remap RTIO to avoid conflict with Ethernet MAC+PHY

Browse Source
This commit is contained in:
Sebastien Bourdeauducq 2014-11-21 15:51:51 -08:00
parent 1f92e19f2b
commit 65567e1201
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
soc/targets/artiq.py
View File

@ -41,7 +41,7 @@ class _TestGen(Module):
class ARTIQMiniSoC(BaseSoC):
csr_map = {
"rtio": 12
"rtio": 13
}
csr_map.update(BaseSoC.csr_map)