forked from M-Labs/artiq
1
0
Fork 0
Commit Graph

6632 Commits

Author SHA1 Message Date
Sebastien Bourdeauducq 59033d2588 firmware: workaround for RPC failures 2018-11-12 19:51:54 +08:00
Sebastien Bourdeauducq 84a6b3d09b runtime: fix DMA recording after now-pinning 2018-11-10 14:14:55 +08:00
Robert Jördens a4997c56cf ad9910: simplify edge detection logic
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-09 18:54:34 +00:00
Robert Jördens e927551827 manual: add highfinesse-net port 2018-11-09 19:39:25 +01:00
Robert Jördens 14b6b63916 ad9910: rewire io_delay tuning
This now reliably locates the SYNC_CLK-IO_UPDATE edge by doing two
scans at different delays between start and stop IO_UPDATE.
It also works well when one delay is very close to the edge.
And it correctly identifies which (start or stop) pulse hit or crossed
the SYNC_CLK edge.

for #1143

Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-09 18:38:27 +00:00
Sebastien Bourdeauducq 1f7858b80b test/dsp: fix rtio_output 2018-11-09 22:11:44 +08:00
Sebastien Bourdeauducq e509ab8553 test/dsp: use absolute import path
Avoids "ImportError: attempted relative import with no known parent package"
when doing a simple "python -m unittest test_XXX.py".
2018-11-09 22:10:46 +08:00
Robert Jördens fe3d6661eb manual: kasli device name for zadig on windows
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-09 15:00:59 +01:00
Robert Jördens 38c6878d49 urukul: mention min/max attenuation
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-09 13:32:05 +01:00
Robert Jördens e565ca6b82 urukul: slow down att write to datasheet limit
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-09 13:23:06 +01:00
Robert Jördens 998be50f07 urukul: handle MSB in att_reg
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-09 13:21:14 +01:00
Sebastien Bourdeauducq c990b5e4f1 Merge remote-tracking branch 'origin/master' into new 2018-11-08 20:21:56 +08:00
Sebastien Bourdeauducq a0cc7311ad test: tighten test_pulse_rate 2018-11-08 20:17:55 +08:00
Sebastien Bourdeauducq 0bee43aa58 sawg: use new rtio_output() API 2018-11-08 20:16:30 +08:00
Sebastien Bourdeauducq bec25cbaa0 suservo: use new rtio_output() API 2018-11-08 20:13:14 +08:00
Sebastien Bourdeauducq e8d58b35b4 spi2: use new rtio_output() API 2018-11-08 20:12:30 +08:00
Sebastien Bourdeauducq d18546550e grabber: use new rtio_output() API 2018-11-08 19:15:50 +08:00
Sebastien Bourdeauducq 2549e623c1 ad9914: use new rtio_output() API 2018-11-08 19:15:44 +08:00
David Nadlinger 9740032a94 firmware: Fix dma_record_output_wide 2018-11-08 11:06:43 +00:00
Sebastien Bourdeauducq f74dda639f drtio: 8-bit address 2018-11-08 18:36:20 +08:00
Sebastien Bourdeauducq 8caea0e6d3 gateware,runtime: optimize RTIO kernel interface further
* now pinning (TODO: atomicity)
* for inputs, merge request and timeout registers
2018-11-08 18:29:24 +08:00
Robert Jördens fcb611d1d2 test_ad9910: don't expect large SYNC_IN delay margins
sinara-hw/Urukul#16

Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-07 18:18:35 +01:00
Sebastien Bourdeauducq aadf5112b7 rtio: remove incorrect comment 2018-11-08 00:02:44 +08:00
Sebastien Bourdeauducq fae95e73ad ttl: use optimized rtio_output API 2018-11-07 23:41:43 +08:00
Sebastien Bourdeauducq 3d0c3cc1cf gateware,runtime: optimize RTIO output interface
* reduce address to 8 bits
* merge core, channel and address into 32-bit pre-computable "target"
* merge we register into data register
2018-11-07 23:39:58 +08:00
Robert Jördens e6efe830c4 ad9910: rewire sync delay tuning
* search from wide window end
* decouple margins and minimum window size
* add note about kasli jitter

Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-07 14:52:03 +00:00
Sebastien Bourdeauducq ad0254c17b Merge branch 'switching125' into new 2018-11-07 22:03:18 +08:00
Sebastien Bourdeauducq efd735a6ab Revert "drtio: monitor RTIOClockMultiplier PLL (#1155)"
This reverts commit 469a66db61.
2018-11-07 22:01:03 +08:00
Robert Jördens 6c00ab57c0 test_ad9910: relax SYNC window
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-06 19:31:38 +01:00
Robert Jördens 172633c7da test_ad9910: default to a useful seed
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-06 17:35:57 +01:00
Robert Jördens 0b2661a34d ad9910: robustify SYNC window finding
don't integrate too long, find the window tip fast and early
a couple 100 SYNC pulses are sufficient

Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-06 12:41:21 +00:00
Robert Jördens ba4bf6e59b kasli: don't pass rtio pll feedback through bufg
UG472: "The MMCM performance increases because the
feedback clock is not subjected to noise on the core supply since it
never passes through a block powered by this supply."

Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-06 11:58:55 +00:00
Robert Jördens b6e4961b0f kasli: lower RTIO clock jitter
* high bandwidth since the si5324 is good
* no low power ibufgds
* drop bufg between ibufgds and pll
* increase pll vco frequency to 1.5 GHz

Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-06 11:43:19 +00:00
Robert Jördens e17e458c58 ptb2: add sync to urukul0 for ad9910 usage
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-06 10:06:51 +00:00
Robert Jördens 73b7124091 test_ad9910: print sync scan for debugging
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-06 10:04:21 +01:00
Sebastien Bourdeauducq 9a3d81ffee kasli: fix tester clk_sel 2018-11-06 14:49:21 +08:00
Sebastien Bourdeauducq fb12df7e01 Revert "kasli_tester: urukul0 mmcx clock defunct"
This reverts commit 68220c316d.
2018-11-06 14:33:21 +08:00
Robert Jördens 31f68ddf6c Merge branch 'urukul-sync'
* urukul-sync: (29 commits)
  urukul: flake8 [nfc]
  ad9910: flake8 [nfc]
  urukul/ad9910 test: remove unused import
  test_urukul: relax speed
  urukul,ad9910: print speed metrics
  kasli: add PTB2 (external clock and SYNC)
  kasli: add sync to LUH, HUB, Opticlock
  kasli_tester: urukul0 mmcx clock defunct
  test_ad9910: relax ifc mode read
  tests: add Urukul-AD9910 HITL unittests including SYNC
  ad9910: add init bit explanation
  test: add Urukul CPLD HITL tests
  ad9910: fiducial timestamp for tracking phase mode
  ad9910: add phase modes
  ad9910: fix pll timeout loop
  tester: add urukul sync
  ptb: back out urukul-sync
  ad9910: add IO_UPDATE alignment and tuning
  urukul: set up sync_in generator
  ad9910: add io_update alignment measurement
  ...

close #1143
2018-11-05 19:54:30 +01:00
Robert Jördens 6fb18270a2 urukul: flake8 [nfc]
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-05 19:45:24 +01:00
Robert Jördens 832690af9a ad9910: flake8 [nfc]
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-05 19:44:51 +01:00
Robert Jördens 6d525e2f9a urukul/ad9910 test: remove unused import
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-05 19:40:57 +01:00
Robert Jördens 36c5a7cd04 test_urukul: relax speed
works fine at < 3µs here but needs <5 µs on buildbot-kasli-tester

Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-05 19:37:20 +01:00
Robert Jördens 89fecfab50 urukul,ad9910: print speed metrics
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-05 19:37:18 +01:00
Robert Jördens 32d538f72b kasli: add PTB2 (external clock and SYNC)
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-05 19:37:16 +01:00
Robert Jördens d8a5951a13 kasli: add sync to LUH, HUB, Opticlock
for #1143, also add missing LUH device db

Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-05 19:37:14 +01:00
Robert Jördens 68220c316d kasli_tester: urukul0 mmcx clock defunct
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-05 19:37:11 +01:00
Robert Jördens 89fadab63d test_ad9910: relax ifc mode read
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-05 19:37:08 +01:00
Robert Jördens f522e211ba tests: add Urukul-AD9910 HITL unittests including SYNC
for #1143

Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-05 19:37:06 +01:00
Robert Jördens 9fb850ae75 ad9910: add init bit explanation
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-05 19:37:02 +01:00
Robert Jördens bc04da15c5 test: add Urukul CPLD HITL tests
for #1143

Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-05 19:37:00 +01:00