Sebastien Bourdeauducq
|
57d633f48e
|
rtio: remove unnecessary attributes
|
2014-12-01 17:47:24 +08:00 |
Sebastien Bourdeauducq
|
cd587e4f12
|
rtio: do housekeeping in gateware
|
2014-12-01 17:32:36 +08:00 |
Sebastien Bourdeauducq
|
99d530e498
|
targets/ARTIQMiniSoC: remove 2 TTL channels to make room in FPGA
|
2014-12-01 17:31:35 +08:00 |
Sebastien Bourdeauducq
|
3a27f49bff
|
frontend/runelf: use new Comm
|
2014-12-01 15:24:38 +08:00 |
Sebastien Bourdeauducq
|
2146e58d20
|
frontend: rename files to avoid conflicts
|
2014-12-01 15:20:35 +08:00 |
Sebastien Bourdeauducq
|
50e0bf3280
|
rtio: optimize flag handling
|
2014-12-01 14:29:50 +08:00 |
Sebastien Bourdeauducq
|
572eecc57b
|
rtio: stricter upper bound on guard time to avoid race condition
|
2014-12-01 14:27:03 +08:00 |
Sebastien Bourdeauducq
|
d50dbc0e73
|
coredevice/runtime_exceptions: update RTIO exception behaviour doc
|
2014-12-01 13:57:25 +08:00 |
Sebastien Bourdeauducq
|
7166ca82d1
|
targets/ARTIQMiniSoC: map RTIO CSRs directly on Wishbone (reduces programming time by 30%)
|
2014-11-30 22:31:55 +08:00 |
Sebastien Bourdeauducq
|
1f6441948d
|
more TTL channels and larger input FIFOs on Papilio Pro
|
2014-11-30 15:50:57 +08:00 |
Sebastien Bourdeauducq
|
e5286c57ab
|
rtio: fix input FIFO depth config
|
2014-11-30 12:12:35 +08:00 |
Sebastien Bourdeauducq
|
bf745e53c9
|
rtio: register FIFO output to improve timing
|
2014-11-30 10:51:12 +08:00 |
Sebastien Bourdeauducq
|
dda4002ae1
|
rtio/phy: fix input synchronization
|
2014-11-30 10:50:48 +08:00 |
Sebastien Bourdeauducq
|
c78c5a2b4f
|
rtio: fix guard cycle computation
|
2014-11-30 01:00:52 +08:00 |
Sebastien Bourdeauducq
|
39c4b5416f
|
targets/ARTIQMiniSoC: 125MHz RTIO clocking
|
2014-11-30 01:00:27 +08:00 |
Sebastien Bourdeauducq
|
9aafe89518
|
rtio: use Record
|
2014-11-30 00:59:39 +08:00 |
Sebastien Bourdeauducq
|
901073acf3
|
asynchronous RTIO
|
2014-11-30 00:13:54 +08:00 |
Sebastien Bourdeauducq
|
9c41f98d70
|
lda_controller: fix memory leak
|
2014-11-29 11:19:03 +08:00 |
Sebastien Bourdeauducq
|
26180e7905
|
manual/drivers_reference: add lda
|
2014-11-29 11:04:13 +08:00 |
Sebastien Bourdeauducq
|
8f18d8d492
|
devices: use underscore in filenames to permit import
|
2014-11-29 11:03:52 +08:00 |
Sebastien Bourdeauducq
|
8593ac85fd
|
doc/manual/writing_a_driver: use underscore in filenames
|
2014-11-29 10:57:23 +08:00 |
Yann Sionneau
|
81ab801fe4
|
lda: filter reports when waiting for command response
|
2014-11-29 10:50:41 +08:00 |
Yann Sionneau
|
075e540032
|
lda: separate simulation class
|
2014-11-29 10:50:12 +08:00 |
Yann Sionneau
|
b9e7fdb80e
|
lda: add docstring
|
2014-11-29 10:49:43 +08:00 |
Sebastien Bourdeauducq
|
44ec3eae3d
|
soc/target: use minicon by default
|
2014-11-28 10:21:43 +08:00 |
Sebastien Bourdeauducq
|
41ecf09873
|
doc/manual/installing: add missing cd
|
2014-11-27 22:27:18 +08:00 |
Sebastien Bourdeauducq
|
6e219469fe
|
py2llvm: support operations between fractions and floats
|
2014-11-27 18:52:45 +08:00 |
Sebastien Bourdeauducq
|
f12389cdd4
|
doc/manual: add controller default TCP port list
|
2014-11-25 20:24:57 +08:00 |
Sebastien Bourdeauducq
|
dc27c2e3ad
|
lda: remove excessive verbosity
|
2014-11-25 19:59:53 +08:00 |
Sebastien Bourdeauducq
|
57e25c7af1
|
lda: minor fixes and refactoring
|
2014-11-25 19:56:28 +08:00 |
Yann Sionneau
|
744e7841c6
|
devices: initial LDA controller
|
2014-11-25 19:51:28 +08:00 |
Sebastien Bourdeauducq
|
a3f981726a
|
units: error checking
|
2014-11-22 16:56:51 -08:00 |
Sebastien Bourdeauducq
|
d59d110f78
|
doc/manual: add ports to index
|
2014-11-21 18:08:40 -08:00 |
Sebastien Bourdeauducq
|
ab88c6d0b8
|
transforms/lower_units: fix bugs and add unit test
|
2014-11-21 18:08:14 -08:00 |
Sebastien Bourdeauducq
|
8d59f843fb
|
doc/manual: add FPGA board info and TTL line assignments
|
2014-11-21 16:39:22 -08:00 |
Sebastien Bourdeauducq
|
35d4f75b65
|
transforms: PEP8
|
2014-11-21 15:55:39 -08:00 |
Sebastien Bourdeauducq
|
65567e1201
|
soc/target: remap RTIO to avoid conflict with Ethernet MAC+PHY
|
2014-11-21 15:51:51 -08:00 |
Sebastien Bourdeauducq
|
1f92e19f2b
|
transforms/fold_constants: support decimal fractions
|
2014-11-21 15:51:20 -08:00 |
Sebastien Bourdeauducq
|
57cc6479c4
|
pyon: fraction support
|
2014-11-21 11:30:37 -08:00 |
Sebastien Bourdeauducq
|
64866a0f49
|
pc_rpc: add init magic string
|
2014-11-20 14:21:41 -08:00 |
Sebastien Bourdeauducq
|
914bdd95d5
|
runtime: use booleans in syscalls
|
2014-11-20 12:49:09 -08:00 |
Sebastien Bourdeauducq
|
dfd779c7c5
|
core: add underflow recovery function
|
2014-11-20 12:38:52 -08:00 |
Sebastien Bourdeauducq
|
96720d20e9
|
examples: remove compiler_test
|
2014-11-20 12:33:55 -08:00 |
Sebastien Bourdeauducq
|
1780759327
|
dds: phase control (mostly untested)
|
2014-11-20 12:32:56 -08:00 |
Sebastien Bourdeauducq
|
e01050b19a
|
transforms/inline: fix default values of positional args
|
2014-11-19 22:55:34 -08:00 |
Sebastien Bourdeauducq
|
b736c30cdb
|
coredevice/core: core_com -> comm
|
2014-11-19 17:44:06 -08:00 |
Sebastien Bourdeauducq
|
75df0ae94a
|
coredevice/gpio: replace set() with on()/off() to make API consistent
|
2014-11-19 12:33:33 -08:00 |
Sebastien Bourdeauducq
|
9098d10766
|
use .py extension on all Python files
|
2014-11-18 13:50:47 -08:00 |
Sebastien Bourdeauducq
|
8b552134a0
|
transforms/inline: keyword argument and default value support
|
2014-11-18 13:40:15 -08:00 |
Sebastien Bourdeauducq
|
abae5c6728
|
coredevice/dds: round FTW instead of flooring
|
2014-11-17 18:36:00 -07:00 |