forked from M-Labs/artiq
dds: phase control (mostly untested)
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e01050b19a
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1780759327
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@ -3,6 +3,12 @@ from artiq.language.units import *
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from artiq.coredevice import rtio
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PHASE_MODE_DEFAULT = -1
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PHASE_MODE_CONTINUOUS = 0
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PHASE_MODE_ABSOLUTE = 1
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PHASE_MODE_TRACKING = 2
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class DDS(AutoContext):
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"""Core device Direct Digital Synthesis (DDS) driver.
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@ -21,6 +27,7 @@ class DDS(AutoContext):
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def build(self):
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self.previous_frequency = 0*MHz
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self.set_phase_mode(PHASE_MODE_CONTINUOUS)
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self.sw = rtio.RTIOOut(self, channel=self.rtio_switch)
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@portable
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@ -40,33 +47,71 @@ class DDS(AutoContext):
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return ftw*self.dds_sysclk/2**32
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@kernel
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def on(self, frequency):
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"""Sets the DDS channel to the specified frequency and turns it on.
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def set_phase_mode(self, phase_mode):
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"""Sets the phase mode of the DDS channel. Supported phase modes are:
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If the DDS channel was already on, a real-time frequency update is
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performed.
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* ``PHASE_MODE_CONTINUOUS``: the phase accumulator is unchanged when
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switching frequencies. The DDS phase is the sum of the phase
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accumulator and the phase offset. The only discrete jumps in the
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DDS output phase come from changes to the phase offset.
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* ``PHASE_MODE_ABSOLUTE``: the phase accumulator is reset when
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switching frequencies. Thus, the phase of the DDS at the time of
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the frequency change is equal to the phase offset.
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* ``PHASE_MODE_TRACKING``: when switching frequencies, the phase
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accumulator is set to the value it would have if the DDS had been
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running at the specified frequency since the start of the
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experiment.
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"""
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self.phase_mode = phase_mode
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syscall("dds_phase_clear_en", self.reg_channel,
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self.phase_mode != PHASE_MODE_CONTINUOUS)
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@kernel
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def on(self, frequency, phase_mode=PHASE_MODE_DEFAULT, phase_offset=0):
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"""Sets the DDS channel to the specified frequency and turns it on.
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If the DDS channel was already on, a real-time frequency and phase
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update is performed.
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:param frequency: frequency to generate.
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:param phase_mode: if specified, overrides the default phase mode set
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by ``set_phase_mode`` for this call.
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:param phase_offset: adds an offset, in turns, to the phase.
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"""
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if phase_mode != PHASE_MODE_DEFAULT:
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old_phase_mode = self.phase_mode
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self.set_phase_mode(phase_mode)
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if self.previous_frequency != frequency:
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merge = self.sw.previous_timestamp == time_to_cycles(now())
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if not merge:
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self.sw.sync()
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if merge or bool(self.sw.previous_value):
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# Channel is already on.
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# Precise timing of frequency change is required.
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fud_time = time_to_cycles(now())
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# Channel is already on:
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# Precise timing of frequency change is required.
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# Channel is off:
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# Use soft timing on FUD to prevent conflicts when reprogramming
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# several channels that need to be turned on at the same time.
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rt_fud = merge or bool(self.sw.previous_value)
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ftw = self.frequency_to_ftw(frequency)
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if self.phase_mode != PHASE_MODE_CONTINUOUS:
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phase_per_microcycle = ftw*int64(
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self.dds_sysclk.amount*self.core.runtime_env.ref_period)
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else:
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# Channel is off.
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# Use soft timing on FUD to prevent conflicts when
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# reprogramming several channels that need to be turned on at
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# the same time.
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fud_time = -1
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syscall("dds_program", self.reg_channel,
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self.frequency_to_ftw(frequency),
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fud_time)
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phase_per_microcycle = int64(0)
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syscall("dds_program", time_to_cycles(now()), self.reg_channel,
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ftw, int(phase_offset*2**14),
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phase_per_microcycle,
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rt_fud, self.phase_mode == PHASE_MODE_TRACKING)
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self.previous_frequency = frequency
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self.sw.on()
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if phase_mode != PHASE_MODE_DEFAULT:
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self.set_phase_mode(old_phase_mode)
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@kernel
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def off(self):
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"""Turns the DDS channel off.
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@ -75,13 +120,16 @@ class DDS(AutoContext):
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self.sw.off()
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@kernel
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def pulse(self, frequency, duration):
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def pulse(self, frequency, duration,
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phase_mode=PHASE_MODE_DEFAULT, phase_offset=0):
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"""Pulses the DDS channel for the specified duration at the specified
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frequency.
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See ``on`` for a description of the parameters.
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Equivalent to a ``on``, ``delay``, ``off`` sequence.
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"""
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self.on(frequency)
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self.on(frequency, phase_mode, phase_offset)
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delay(duration)
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self.off()
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@ -19,17 +19,20 @@ _syscalls = {
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"rtio_sync": "i:n",
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"rtio_get": "i:I",
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"rtio_pileup_count": "i:i",
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"dds_program": "iiI:n",
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"dds_phase_clear_en": "ib:n",
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"dds_program": "IiiiIbb:n",
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}
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_chr_to_type = {
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"n": lambda: lc.Type.void(),
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"b": lambda: lc.Type.int(1),
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"i": lambda: lc.Type.int(32),
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"I": lambda: lc.Type.int(64)
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}
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_chr_to_value = {
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"n": lambda: base_types.VNone(),
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"b": lambda: base_types.VBool(),
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"i": lambda: base_types.VInt(),
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"I": lambda: base_types.VInt(64)
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}
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@ -9,6 +9,8 @@
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#define DDS_FTW1 0x0b
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#define DDS_FTW2 0x0c
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#define DDS_FTW3 0x0d
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#define DDS_POW0 0x0e
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#define DDS_POW1 0x0f
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#define DDS_GPIO 0x41
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#define DDS_READ(addr) \
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@ -25,22 +27,55 @@ void dds_init(void)
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DDS_WRITE(DDS_GPIO, i);
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DDS_WRITE(DDS_GPIO, i | (1 << 7));
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DDS_WRITE(DDS_GPIO, i);
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DDS_WRITE(0x00, 0x78);
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DDS_WRITE(0x01, 0x00);
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DDS_WRITE(0x02, 0x00);
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DDS_WRITE(0x03, 0x00);
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rtio_fud(-1);
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rtio_fud_sync();
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dds_phase_clear_en(i, 0);
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}
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}
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void dds_program(int channel, int ftw, long long int fud_time)
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void dds_phase_clear_en(int channel, int phase_clear_en)
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{
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DDS_WRITE(0x00, 0x78);
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DDS_WRITE(0x01, 0x00);
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DDS_WRITE(0x02, phase_clear_en ? 0x40 : 0x00);
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DDS_WRITE(0x03, 0x00);
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}
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/*
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* DDS phase modes:
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* - continuous: Set phase_per_microcycle=0 to disable POW alteration.
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* phase_tracking is ignored, set to 0.
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* Disable phase accumulator clearing prior to programming.
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* - absolute: Set phase_per_microcycle to its nominal value
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* and phase_tracking=0.
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* Enable phase accumulator clearing prior to programming.
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* - tracking: Set phase_per_microcycle to its nominal value
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* and phase_tracking=1.
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* Enable phase accumulator clearing prior to programming.
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*/
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void dds_program(long long int timestamp, int channel,
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int ftw, int pow, long long int phase_per_microcycle,
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int rt_fud, int phase_tracking)
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{
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long long int fud_time;
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long long int phase_time_offset;
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rtio_fud_sync();
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DDS_WRITE(DDS_GPIO, channel);
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DDS_WRITE(DDS_FTW0, ftw & 0xff);
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DDS_WRITE(DDS_FTW1, (ftw >> 8) & 0xff);
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DDS_WRITE(DDS_FTW2, (ftw >> 16) & 0xff);
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DDS_WRITE(DDS_FTW3, (ftw >> 24) & 0xff);
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phase_time_offset = phase_tracking ? timestamp : 0;
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if(rt_fud)
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fud_time = timestamp;
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else {
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fud_time = rtio_get_counter() + 8000;
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phase_time_offset -= timestamp - fud_time;
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}
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pow += phase_time_offset*phase_per_microcycle;
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DDS_WRITE(DDS_POW0, pow & 0xff);
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DDS_WRITE(DDS_POW1, (pow >> 8) & 0x3f);
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rtio_fud(fud_time);
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}
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@ -2,6 +2,9 @@
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#define __DDS_H
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void dds_init(void);
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void dds_program(int channel, int ftw, long long int fud_time);
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void dds_phase_clear_en(int channel, int phase_clear_en);
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void dds_program(long long int timestamp, int channel,
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int ftw, int pow, long long int phase_per_microcycle,
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int rt_fud, int phase_tracking);
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#endif /* __DDS_H */
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@ -110,7 +110,6 @@ int main(void)
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uart_init();
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puts("ARTIQ runtime built "__DATE__" "__TIME__"\n");
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rtio_init();
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dds_init();
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blink_led();
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comm_serve(load_object, run_kernel);
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@ -10,6 +10,7 @@ void rtio_init(void)
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previous_fud_end_time = 0;
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rtio_reset_counter_write(1);
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rtio_reset_logic_write(1);
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rtio_reset_counter_write(0);
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rtio_reset_logic_write(0);
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}
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@ -21,7 +22,6 @@ void rtio_oe(int channel, int oe)
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void rtio_set(long long int timestamp, int channel, int value)
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{
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rtio_reset_counter_write(0);
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rtio_chan_sel_write(channel);
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rtio_o_timestamp_write(timestamp);
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rtio_o_value_write(value);
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@ -53,6 +53,12 @@ void rtio_sync(int channel)
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while(rtio_o_level_read() != 0);
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}
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long long int rtio_get_counter(void)
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{
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rtio_counter_update_write(1);
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return rtio_counter_read();
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}
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long long int rtio_get(int channel)
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{
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long long int r;
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@ -94,12 +100,7 @@ void rtio_fud(long long int fud_time)
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{
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long long int fud_end_time;
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rtio_reset_counter_write(0);
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rtio_chan_sel_write(RTIO_FUD_CHANNEL);
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if(fud_time < 0) {
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rtio_counter_update_write(1);
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fud_time = rtio_counter_read() + 4000;
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}
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fud_end_time = fud_time + 3*8;
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if(fud_time < previous_fud_end_time)
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exception_raise(EID_RTIO_SEQUENCE_ERROR);
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@ -6,6 +6,7 @@ void rtio_oe(int channel, int oe);
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void rtio_set(long long int timestamp, int channel, int value);
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void rtio_replace(long long int timestamp, int channel, int value);
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void rtio_sync(int channel);
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long long int rtio_get_counter(void);
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long long int rtio_get(int channel);
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int rtio_pileup_count(int channel);
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@ -17,6 +17,7 @@ static const struct symbol syscalls[] = {
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{"rtio_sync", rtio_sync},
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{"rtio_get", rtio_get},
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{"rtio_pileup_count", rtio_pileup_count},
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{"dds_phase_clear_en", dds_phase_clear_en},
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{"dds_program", dds_program},
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{NULL, NULL}
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};
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