proto FW: add memory write test

proto FW: fix compilation error

src/gateware/cxp.py

@@ -1,276 +1,153 @@
 from migen import *
-from migen.genlib.cdc import MultiReg, PulseSynchronizer
 from misoc.interconnect.csr import *
+from misoc.interconnect import stream
 
-from cxp_downconn import CXP_DownConn_PHYS
+from cxp_downconn import CXP_DownConn_PHY
-from cxp_upconn import CXP_UpConn_PHYS
+from cxp_upconn import CXP_UpConn_PHY
 from cxp_pipeline import *
 
-
+buffer_depth = 128
-class CXP_PHYS(Module, AutoCSR):
-    def __init__(self, refclk, upconn_pads, downconn_pads, sys_clk_freq, debug_sma, pmod_pads):
-        assert len(upconn_pads) == len(downconn_pads)
-        self.submodules.upconn = CXP_UpConn_PHYS(upconn_pads, sys_clk_freq, debug_sma, pmod_pads)
-        self.submodules.downconn = CXP_DownConn_PHYS(refclk, downconn_pads, sys_clk_freq, debug_sma, pmod_pads)
 
 @FullMemoryWE()
-class CXP_Interface(Module, AutoCSR):
+class CXP(Module, AutoCSR):
-    def __init__(self, upconn_phy, downconn_phy, debug_sma, pmod_pads):
+    def __init__(self, refclk, downconn_pads, upconn_pads, sys_clk_freq, debug_sma, pmod_pads):
-        # TODO: move all transceiver csr into a transceiver interface submodule
+        self.submodules.upconn = UpConn_Interface(upconn_pads, sys_clk_freq, debug_sma, pmod_pads)
 
-        self.submodules.upconn = UpConn_Interface(upconn_phy, debug_sma, pmod_pads)
+        self.submodules.downconn = DownConn_Interface(refclk, downconn_pads, sys_clk_freq, debug_sma, pmod_pads)
+        # TODO: support the option high speed upconn
 
-        self.submodules.downconn = DownConn_Interface(downconn_phy, debug_sma, pmod_pads)
+        self.submodules.transmitter = Transmitter()
+
+        # TODO: add link layer
 
     def get_tx_port(self):
-        return self.upconn.command.mem.get_port(write_capable=True)
+        return self.transmitter.mem.get_port(write_capable=True)
-
-    def get_rx_port(self):
-        return self.downconn.packet_decoder.mem.get_port(write_capable=False)
-
-    def get_loopback_tx_port(self):
-        return self.downconn.command.mem.get_port(write_capable=True)
     
     def get_mem_size(self):
-        return buffer_depth*word_dw
+        return buffer_depth*downconn_dw
 
-class DownConn_Interface(Module, AutoCSR):
+@FullMemoryWE()
-    def __init__(self, phy, debug_sma, pmod_pads):
+class Transmitter(Module, AutoCSR):
-        self.rx_start_init = CSRStorage()
+    def __init__(self):
-        self.rx_restart = CSR()
+        self.cxp_tx_word_len = CSRStorage(bits_for(buffer_depth))
-        self.rx_ready = CSRStatus()
+        self.cxp_tx = CSR()
 
         # # #
         
-        gtx = phy.gtx
+        self.specials.mem = mem = Memory(downconn_dw, buffer_depth)
+        self.specials.mem_port = mem_port = mem.get_port()
+        self.source = stream.Endpoint(downconn_layout)
 
-        # GTX Control
+
+        tx_done = Signal()
+        addr_next = Signal(bits_for(buffer_depth))
+        addr = Signal.like(addr_next)
+        addr_rst = Signal()
+        addr_inc = Signal()
+
+        # increment addr in the same cycle the moment addr_inc is rise
+        # since memory takes one cycle to shift to the correct addr
         self.sync += [
-            gtx.rx_restart.eq(self.rx_restart.re),
+            addr.eq(addr_next),
-            gtx.rx_init.clk_path_ready.eq(self.rx_start_init.storage),
+            If(self.cxp_tx.re, self.cxp_tx.w.eq(1)),
-            self.rx_ready.status.eq(gtx.rx_ready),
+            If(tx_done, self.cxp_tx.w.eq(0)),
         ]
 
-
-        # DEBUG: tx control
-        self.tx_start_init = CSRStorage()
-        self.tx_restart = CSR()
-        self.txenable = CSRStorage()
-        self.sync += [
-            gtx.txenable.eq(self.txenable.storage),
-            gtx.tx_restart.eq(self.tx_restart.re),
-            gtx.tx_init.clk_path_ready.eq(self.tx_start_init.storage),
-        ]
-
-        # DEBUG: loopback control
-        self.loopback_mode = CSRStorage(3)
-        self.comb += gtx.loopback_mode.eq(self.loopback_mode.storage) 
-
-        
-        # DEBUG: init status
-        self.txinit_phaligndone = CSRStatus()
-        self.rxinit_phaligndone = CSRStatus()
-        self.comb += [
-            self.txinit_phaligndone.status.eq(gtx.tx_init.Xxphaligndone),
-            self.rxinit_phaligndone.status.eq(gtx.rx_init.Xxphaligndone),
-        ]
-
-        # Connect all GTX connections' DRP
-        self.gtx_daddr = CSRStorage(9)
-        self.gtx_dread = CSR()
-        self.gtx_din_stb = CSR()
-        self.gtx_din = CSRStorage(16)
-
-        self.gtx_dout = CSRStatus(16)
-        self.gtx_dready = CSR()
-
-        self.comb += gtx.dclk.eq(ClockSignal("sys"))
-        self.sync += [
-            gtx.den.eq(0),
-            gtx.dwen.eq(0),
-            If(self.gtx_dread.re,
-                gtx.den.eq(1),
-                gtx.daddr.eq(self.gtx_daddr.storage),
-            ).Elif(self.gtx_din_stb.re,
-                gtx.den.eq(1),
-                gtx.dwen.eq(1),
-                gtx.daddr.eq(self.gtx_daddr.storage),
-                gtx.din.eq(self.gtx_din.storage),
-            ),
-            If(gtx.dready,
-               self.gtx_dready.w.eq(1),
-               self.gtx_dout.status.eq(gtx.dout),
-            ),
-            If(self.gtx_dready.re,
-               self.gtx_dready.w.eq(0),
-            ),
-        ]
-
-
-        # DEBUG: txusrclk PLL DRP
-        
-        self.txpll_reset = CSRStorage()
-        self.pll_daddr = CSRStorage(7)
-        self.pll_dclk = CSRStorage()
-        self.pll_den = CSRStorage()
-        self.pll_din = CSRStorage(16)
-        self.pll_dwen = CSRStorage()
-
-        self.txpll_locked = CSRStatus()
-        self.pll_dout = CSRStatus(16)
-        self.pll_dready = CSRStatus()
-
         self.comb += [
-            gtx.txpll_reset.eq(self.txpll_reset.storage),
+            addr_next.eq(addr),
-            gtx.pll_daddr.eq(self.pll_daddr.storage),
+            If(addr_rst,
-            gtx.pll_dclk.eq(self.pll_dclk.storage),
+                addr_next.eq(addr_next.reset),
-            gtx.pll_den.eq(self.pll_den.storage),
+            ).Elif(addr_inc,
-            gtx.pll_din.eq(self.pll_din.storage),
+                addr_next.eq(addr + 1),
-            gtx.pll_dwen.eq(self.pll_dwen.storage),
+            ),
-
+            mem_port.adr.eq(addr_next),
-            self.txinit_phaligndone.status.eq(gtx.tx_init.Xxphaligndone),
+            self.source.data.eq(mem_port.dat_r)
-            self.rxinit_phaligndone.status.eq(gtx.rx_init.Xxphaligndone),
-            self.txpll_locked.status.eq(gtx.txpll_locked),
-            self.pll_dout.status.eq(gtx.pll_dout),
-            self.pll_dready.status.eq(gtx.pll_dready),
         ]
 
+        self.submodules.fsm = fsm = FSM(reset_state="IDLE")
 
-        # DEBUG: tx loopback fifo control
+        fsm.act("IDLE",
-        self.tx_stb = CSRStorage()
+            addr_rst.eq(1),
-        self.sync += phy.tx_stb_sys.eq(self.tx_stb.storage) 
+            If(self.cxp_tx.re, NextState("TRANSMIT"))
+        )
+        fsm.act("TRANSMIT",
+            self.source.stb.eq(1),
+            If(self.source.ack,
+                addr_inc.eq(1),
+            ),
+            If(addr_next == self.cxp_tx_word_len.storage,
+                tx_done.eq(1),
+                NextState("IDLE")
+            )
+        )
 
+        self.submodules.debug_out = debug_out = RX_Debug_Buffer()
+        self.comb += self.source.connect(debug_out.sink)
 
-        # DEBUG: Transmission Pipeline
+class DownConn_Interface(Module, AutoCSR):
-        # 
+    def __init__(self, refclk, downconn_pads, sys_clk_freq, debug_sma, pmod_pads):
-        # test pak ----+
+        # # #
-        # from gw      |   32                                            32
-        #              |---/---> mux -----> packet -----> trigger ack ---/---> PHY
-        #              |                    wrapper       inserter
-        # data pak ----+
-        # from fw
 
+        self.submodules.phy = phy = CXP_DownConn_PHY(refclk, downconn_pads, sys_clk_freq, debug_sma, pmod_pads)
+        self.gtxs = phy.gtxs
 
         # DEBUG: TX pipeline
-        self.submodules.command = command = TX_Command_Packet()
+        self.submodules.debug_src = debug_src = TX_Command_Packet()
+        self.submodules.trig_ack = trig_ack = Trigger_ACK()
         self.submodules.testseq = testseq = TX_Test_Packet()
-        self.submodules.mux = mux = stream.Multiplexer(word_layout, 2)
+        self.submodules.mux = mux = stream.Multiplexer(upconn_layout, 3)
-        self.submodules.pak_wrp = pak_wrp = Packet_Wrapper()
+        self.submodules.conv = conv = stream.StrideConverter(upconn_layout, downconn_layout)
-        self.submodules.trig_ack = trig_ack = Trigger_ACK_Inserter()
 
         self.ack = CSR()
-        self.mux_sel = CSRStorage()
+        self.mux_sel = CSRStorage(4)
+        self.sync += trig_ack.ack.eq(self.ack.re),
 
-        self.sync += trig_ack.stb.eq(self.ack.re),
         self.comb += [
-            command.source.connect(mux.sink0),
+            debug_src.source.connect(mux.sink0),
-            testseq.source.connect(mux.sink1),
+            trig_ack.source.connect(mux.sink1),
-            mux.sel.eq(self.mux_sel.storage),
+            testseq.source.connect(mux.sink2),
+            mux.sel.eq(self.mux_sel.storage)
         ]
 
-        tx_pipeline = [mux , pak_wrp, trig_ack, phy]
+        tx_pipeline = [mux , conv, phy.sinks[0]]
         for s, d in zip(tx_pipeline, tx_pipeline[1:]):
             self.comb += s.source.connect(d.sink)
 
-
+        # NOTE: RX pipeline
-
-
-        # Receiver Pipeline WIP
-        # 
-        #        32                32
-        # PHY ---/---> CDC FIFO ---/---> trigger ack ------> packet  ------> debug buffer
-        #                                checker             decoder
-        #
-        cdr = ClockDomainsRenamer("cxp_gtx_rx")
-
-        # Priority level 1 packet - Trigger ack packet
-        self.submodules.trig_ack_checker = trig_ack_checker = cdr(CXP_Trig_Ack_Checker())
-        
-        self.submodules.trig_ack_ps = trig_ack_ps = PulseSynchronizer("cxp_gtx_rx", "sys")
-        self.comb += trig_ack_ps.i.eq(trig_ack_checker.ack)
-
-        self.trig_ack = Signal()
-        self.trig_clr = Signal()
-        # Error are latched
-        self.sync += [
-            If(trig_ack_ps.o,
-                self.trig_ack.eq(1),
-            ).Elif(self.trig_clr,
-                self.trig_ack.eq(0),
-            ),
-        ]
-
-        # Priority level 2 packet - data, test packet
-        self.submodules.packet_decoder = packet_decoder = cdr(CXP_Data_Packet_Decode())
-
-        self.new_rx_packet = CSR()
-        self.decoder_error = CSR()
-        self.test_error = CSR()
-
-        self.submodules.new_packet_ps = new_packet_ps = PulseSynchronizer("cxp_gtx_rx", "sys")
-        self.submodules.decode_err_ps = decode_err_ps = PulseSynchronizer("cxp_gtx_rx", "sys")
-        self.submodules.test_err_ps = test_err_ps = PulseSynchronizer("cxp_gtx_rx", "sys")
-        self.comb += [
-            new_packet_ps.i.eq(packet_decoder.new_packet),
-            decode_err_ps.i.eq(packet_decoder.decode_err),
-            test_err_ps.i.eq(packet_decoder.test_err),
-        ]
-        self.sync += [
-            If(new_packet_ps.o,
-                self.new_rx_packet.w.eq(1),
-            ).Elif(self.new_rx_packet.re,
-                self.new_rx_packet.w.eq(0),
-            ),
-            If(decode_err_ps.o,
-                self.decoder_error.w.eq(1),
-            ).Elif(self.decoder_error.re,
-                self.decoder_error.w.eq(0),
-            ),
-            If(test_err_ps.o,
-                self.test_error.w.eq(1),
-            ).Elif(self.test_error.re,
-                self.test_error.w.eq(0),
-            ),
-        ]
-
-
-        # Cicular buffer interface
-        self.packet_type = CSRStatus(8)
-        self.write_pointer = CSRStatus(bits_for(buffer_depth)) # for firmware to sync with buffer
-
-        self.specials += [
-            MultiReg(packet_decoder.packet_type, self.packet_type.status),
-            MultiReg(packet_decoder.write_ptr, self.write_pointer.status),
-        ]
-
-        # DEBUG: remove this cdc fifo
-        cdc_fifo = stream.AsyncFIFO(word_layout, 512)
-        self.submodules += ClockDomainsRenamer({"write": "cxp_gtx_rx", "read": "sys"})(cdc_fifo)
         self.submodules.debug_out = debug_out = RX_Debug_Buffer()
+        self.submodules.recv_path = recv_path = Receiver_Path()
 
-
+        rx_pipeline = [phy.sources[0], recv_path, debug_out]
-        rx_pipeline = [phy, trig_ack_checker, packet_decoder, cdc_fifo, debug_out]
         for s, d in zip(rx_pipeline, rx_pipeline[1:]):
             self.comb += s.source.connect(d.sink)
 
 
+        self.packet_type = CSRStatus(8)
+        self.decoder_error = CSRStatus()
+        self.test_error = CSRStatus()
+        self.comb += [
+            self.packet_type.status.eq(recv_path.packet_type),
+            self.decoder_error.status.eq(recv_path.decoder_err),
+            self.test_error.status.eq(recv_path.test_err),
+        ]
+        
         # DEBUG: CSR
-        self.trigger_ack = CSR()
+        self.trig_ack = CSRStatus()
-        self.sync += [
+        self.trig_clr = CSR()
-            self.trig_clr.eq(self.trigger_ack.re),
+        self.comb += [
-            self.trigger_ack.w.eq(self.trig_ack),
+            self.trig_ack.status.eq(recv_path.trig_ack),
+            recv_path.trig_clr.eq(self.trig_clr.re),
         ]
 
         pak_start = Signal()
         self.sync += [
-            pak_start.eq(packet_decoder.sink.data == 0xFBFBFBFB),
+            pak_start.eq(recv_path.packet_decoder.sink.data == 0xFBFBFBFB),
+            
         ]
 
         self.specials += [
-            Instance("OBUF", i_I=phy.gtx.cd_cxp_gtx_rx.clk, o_O=debug_sma.p_tx),
-            # Instance("OBUF", i_I=, o_O=debug_sma.p_rx),
             # # pmod 0-7 pin
-            Instance("OBUF", i_I=packet_decoder.test_err, o_O=pmod_pads[0]),
+            Instance("OBUF", i_I=recv_path.packet_decoder.test_err, o_O=pmod_pads[0]),
             Instance("OBUF", i_I=pak_start, o_O=pmod_pads[1]),
             # Instance("OBUF", i_I=fifo_in.source.ack, o_O=pmod_pads[2]),
             # Instance("OBUF", i_I=gtx.comma_checker.aligner_en, o_O=pmod_pads[3]),
@@ -282,103 +159,73 @@ class DownConn_Interface(Module, AutoCSR):
 
         
 class UpConn_Interface(Module, AutoCSR):
-    def __init__(self, phy, debug_sma, pmod_pads):
+    def __init__(self, upconn_pads, sys_clk_freq, debug_sma, pmod_pads):
         self.clk_reset = CSRStorage(reset=1)
         self.bitrate2x_enable = CSRStorage()
         self.tx_enable = CSRStorage()
-
-        # TODO: add busy condition
         self.tx_busy = CSRStatus()
 
         self.tx_testmode_en = CSRStorage()
 
         # # #
 
+        self.submodules.phy = phy = CXP_UpConn_PHY(upconn_pads, sys_clk_freq, debug_sma, pmod_pads)
+
         self.sync += [
             phy.bitrate2x_enable.eq(self.bitrate2x_enable.storage),
             phy.tx_enable.eq(self.tx_enable.storage),
             phy.clk_reset.eq(self.clk_reset.re),
+            self.tx_busy.status.eq(phy.tx_busy),
         ]
 
 
-        # Transmission Pipeline
+        # TODO: rewrite the transmite path into pipeline
         #
         # test pak ----+
         # from gw      |   32                                            32           8
-        #              |---/---> mux -----> packet -----> idle word -----> trigger ack ---/--> conv ---/---> trigger -----> PHY
+        #              |---/---> mux -----> trig ack -----> idle word ---/--> conv ---/---> trig -----> PHY
-        #              |                    wrapper       inserter         inserter                          inserter
+        #              |                    inserter        inserter                       inserter
         # data pak ----+
         # from fw
-        #
-        # Equivalent transmission priority:
-        # trigger > trigger ack > idle > test/data packet
-        # To maintain the trigger performance, idle word should not be inserted into trigger or trigger ack.
-        # 
-        # In low speed CoaXpress, the higher priority packet can be inserted in two types of boundary
-        # Insertion @ char boundary: Trigger packets
-        # Insertion @ word boundary: Trigger ack & IDLE packets
-        # The 32 bit part of the pipeline handles the word boundary insertion while the 8 bit part handles the char boundary insertion
-        
-
 
         # Packet FIFOs with transmission priority
         # 0: Trigger packet
         self.submodules.trig = trig = TX_Trigger()
+        self.comb += trig.source.connect(phy.sinks[0])
         
-        # # DEBUG: INPUT
+        # DEBUG: INPUT
         self.trig_stb = CSR()
         self.trig_delay = CSRStorage(8) 
         self.linktrigger = CSRStorage(2)
 
         self.sync += [
-            trig.stb.eq(self.trig_stb.re),
+            trig.trig_stb.eq(self.trig_stb.re),
             trig.delay.eq(self.trig_delay.storage),
             trig.linktrig_mode.eq(self.linktrigger.storage),
         ]
 
         
         # 1: IO acknowledgment for trigger packet
-        self.submodules.trig_ack = trig_ack = Trigger_ACK_Inserter()
+        self.submodules.trig_ack = trig_ack = Trigger_ACK()
+        self.comb += trig_ack.source.connect(phy.sinks[1])
 
         # DEBUG: INPUT
         self.ack = CSR()
-        self.sync += trig_ack.stb.eq(self.ack.re),
+        self.sync += trig_ack.ack.eq(self.ack.re),
 
 
-        # 2: All other packets (data & test packet)
+        # 2: All other packets
-        # Control is not timing dependent, all the data packets are handled in firmware
+        # Control is not timing dependent, all the link layer is done in firmware
-
         self.submodules.command = command = TX_Command_Packet()
         self.submodules.testseq = testseq = TX_Test_Packet()
-        self.submodules.mux = mux = stream.Multiplexer(word_layout, 2)
+
+
+        self.submodules.mux = mux = stream.Multiplexer(upconn_layout, 2)
 
         self.comb += [
             command.source.connect(mux.sink0),
             testseq.source.connect(mux.sink1),
             mux.sel.eq(self.tx_testmode_en.storage),
+
+            mux.source.connect(phy.sinks[2])
         ]
-
-        self.submodules.pak_wrp = pak_wrp = Packet_Wrapper()
-
-        # IDLE Word
-        self.submodules.idle = idle = Idle_Word_Inserter()
-
-        # Section 9.2.5.1 (CXP-001-2021)
-        # IDLE should be transmitter every 10000 words
-        cnt = Signal(max=10000)
-
-        self.sync += [
-            idle.stb.eq(0),
-            If((~idle.sink.stb) | (cnt == 9999),
-               idle.stb.eq(1),
-               cnt.eq(cnt.reset),
-            ).Else(
-               cnt.eq(cnt + 1),
-            ),
-        ]
-        
-        self.submodules.converter = converter = stream.StrideConverter(word_layout, char_layout)
-
-        tx_pipeline = [mux, pak_wrp, idle, trig_ack, converter, trig, phy]
-        for s, d in zip(tx_pipeline, tx_pipeline[1:]):
-            self.comb += s.source.connect(d.sink)

src/gateware/cxp_downconn.py

@@ -7,20 +7,29 @@ from misoc.interconnect.csr import *
 from misoc.interconnect import stream
 
 from artiq.gateware.drtio.transceiver.gtx_7series_init import *
-from cxp_pipeline import word_layout
+from cxp_pipeline import downconn_layout
 
 from functools import reduce
 from operator import add
 
-class CXP_DownConn_PHYS(Module, AutoCSR):
+class CXP_DownConn_PHY(Module, AutoCSR):
     def __init__(self, refclk, pads, sys_clk_freq, debug_sma, pmod_pads):
+        nconn = len(pads)
+        self.rx_start_init = CSRStorage()
+        self.rx_restart = CSR()
+
+        self.tx_start_init = CSRStorage()
+        self.tx_restart = CSR()
+        self.txenable = CSRStorage()
+
+        self.rx_ready = CSRStatus(nconn)
+
         self.qpll_reset = CSR()
         self.qpll_locked = CSRStatus()
 
-        self.rx_phys = []
+        self.gtxs = []
         # # #
 
-        # For speed higher than 6.6Gbps, QPLL need to be used instead of CPLL
         self.submodules.qpll = qpll = QPLL(refclk, sys_clk_freq)
         self.sync += [
             qpll.reset.eq(self.qpll_reset.re),
@@ -28,10 +37,13 @@ class CXP_DownConn_PHYS(Module, AutoCSR):
         ]
 
 
-        for i, pad in enumerate(pads):
+
-            rx = Receiver(qpll, pad, sys_clk_freq, "single", "single", debug_sma, pmod_pads)
+        for i in range(nconn):
-            self.rx_phys.append(rx)
+            if i != 0:
-            setattr(self.submodules, "rx"+str(i), rx)
+                break
+            gtx = GTX(self.qpll, pads[i], sys_clk_freq, tx_mode="single", rx_mode="single")
+            self.gtxs.append(gtx)
+            setattr(self.submodules, "gtx"+str(i), gtx)
 
             # TODO: add extension gtx connections
             # TODO: add connection interface
@@ -40,32 +52,126 @@ class CXP_DownConn_PHYS(Module, AutoCSR):
         # checkout channel interfaces & drtio_gtx
         # GTPTXPhaseAlignement for inspiration
 
+        # Connect all GTX connections' DRP
 
-class Receiver(Module):
+        self.gtx_daddr = CSRStorage(9)
-    def __init__(self, qpll, pad, sys_clk_freq, tx_mode, rx_mode, debug_sma, pmod_pads):
+        self.gtx_dread = CSR()
-        self.submodules.gtx = gtx = GTX(qpll, pad, sys_clk_freq, tx_mode="single", rx_mode="single")
+        self.gtx_din_stb = CSR()
+        self.gtx_din = CSRStorage(16)
 
-        self.source = stream.Endpoint(word_layout)
+        self.gtx_dout = CSRStatus(16)
+        self.gtx_dready = CSR()
 
-        self.sync.cxp_gtx_rx += [
+        for gtx in self.gtxs:
-            self.source.stb.eq(0),
+            self.sync += [
-            If(gtx.rx_ready & self.source.ack & ~((gtx.decoders[0].d == 0xBC) & (gtx.decoders[0].k == 1)),
+
-                self.source.stb.eq(1),
+                gtx.txenable.eq(self.txenable.storage[0]),
-                self.source.data.eq(Cat(gtx.decoders[0].d, gtx.decoders[1].d, gtx.decoders[2].d, gtx.decoders[3].d)),
+                gtx.tx_restart.eq(self.tx_restart.re),
-                self.source.k.eq(Cat(gtx.decoders[0].k, gtx.decoders[1].k, gtx.decoders[2].k, gtx.decoders[3].k)),
+                gtx.rx_restart.eq(self.rx_restart.re),
-            )
+                gtx.tx_init.clk_path_ready.eq(self.tx_start_init.storage),
+                gtx.rx_init.clk_path_ready.eq(self.rx_start_init.storage),
             ]
 
-        # DEBUG: tx fifos for loopback
+            self.comb += gtx.dclk.eq(ClockSignal("sys"))
+            self.sync += [
+                gtx.den.eq(0),
+                gtx.dwen.eq(0),
+                If(self.gtx_dread.re,
+                    gtx.den.eq(1),
+                    gtx.daddr.eq(self.gtx_daddr.storage),
+                ).Elif(self.gtx_din_stb.re,
+                    gtx.den.eq(1),
+                    gtx.dwen.eq(1),
+                    gtx.daddr.eq(self.gtx_daddr.storage),
+                    gtx.din.eq(self.gtx_din.storage),
+                ),
+            ]
+
+        # TODO: deal with 4 GTX instance of outpus
+        for n, gtx in enumerate(self.gtxs):
+            self.sync += [
+                self.rx_ready.status[n].eq(gtx.rx_ready),
+                If(gtx.dready,
+                   self.gtx_dready.w.eq(1),
+                   self.gtx_dout.status.eq(gtx.dout),
+                ),
+                If(self.gtx_dready.re,
+                   self.gtx_dready.w.eq(0),
+                ),
+            ]
+
+        self.sources = []
+        
+        for n, gtx in enumerate(self.gtxs):
+            # DEBUG: remove cdc fifo
+            # gtx rx -> fifo out -> cdc out
+            
+            fifo_out = stream.AsyncFIFO(downconn_layout, 512)
+            self.submodules += ClockDomainsRenamer({"write": "cxp_gtx_rx", "read": "sys"})(fifo_out)
+            self.sources.append(fifo_out)
+
+            for i in range(4):
+                self.sync.cxp_gtx_rx += [
+                    fifo_out.sink.stb.eq(0),
+                    # don't store idle word in fifo
+                    If((gtx.rx_ready & fifo_out.sink.ack &  ~((gtx.decoders[0].d == 0xBC) & (gtx.decoders[0].k == 1))),
+                        fifo_out.sink.stb.eq(1),
+                        fifo_out.sink.data[i*8:(i*8)+8].eq(gtx.decoders[i].d),
+                        fifo_out.sink.k[i].eq(gtx.decoders[i].k),
+                    ),
+                ]
+        
+
+
+        # DEBUG: tx of gtx is not used in CXP            
+        # DEBUG: txusrclk PLL DRG
+        
+        self.txpll_reset = CSRStorage()
+        self.pll_daddr = CSRStorage(7)
+        self.pll_dclk = CSRStorage()
+        self.pll_den = CSRStorage()
+        self.pll_din = CSRStorage(16)
+        self.pll_dwen = CSRStorage()
+
+        self.txpll_locked = CSRStatus()
+        self.pll_dout = CSRStatus(16)
+        self.pll_dready = CSRStatus()
+
+        self.txinit_phaligndone = CSRStatus()
+        self.rxinit_phaligndone = CSRStatus()
+
+        self.tx_stb = CSRStorage()
+        self.sinks = []
+
+        for n, gtx in enumerate(self.gtxs):
+            self.comb += [
+                gtx.txpll_reset.eq(self.txpll_reset.storage),
+                gtx.pll_daddr.eq(self.pll_daddr.storage),
+                gtx.pll_dclk.eq(self.pll_dclk.storage),
+                gtx.pll_den.eq(self.pll_den.storage),
+                gtx.pll_din.eq(self.pll_din.storage),
+                gtx.pll_dwen.eq(self.pll_dwen.storage),
+
+                self.txinit_phaligndone.status.eq(gtx.tx_init.Xxphaligndone),
+                self.rxinit_phaligndone.status.eq(gtx.rx_init.Xxphaligndone), self.txpll_locked.status.eq(gtx.txpll_locked),
+                self.pll_dout.status.eq(gtx.pll_dout),
+                self.pll_dready.status.eq(gtx.pll_dready),
+            ]
+
+            # DEBUG:loopback 
+            self.loopback_mode = CSRStorage(3)
+            self.comb += gtx.loopback_mode.eq(self.loopback_mode.storage) 
+
+            # DEBUG: datain
             # fw -> fifo (sys) -> cdc fifo -> gtx tx
             
-        tx_fifo = stream.AsyncFIFO(word_layout, 512)
+            fifo_in = stream.AsyncFIFO(downconn_layout, 512)
-        self.submodules += ClockDomainsRenamer({"write": "sys", "read": "cxp_gtx_tx"})(tx_fifo)
+            self.submodules += ClockDomainsRenamer({"write": "sys", "read": "cxp_gtx_tx"})(fifo_in)
-        self.sink = tx_fifo.sink
+            self.sinks.append(fifo_in)
         
-        self.tx_stb_sys = Signal()
+            # TODO: why there this send an extra 0xFB word
             txstb = Signal()
-        self.specials += MultiReg(self.tx_stb_sys, txstb, odomain="cxp_gtx_tx")
+            self.specials += MultiReg(self.tx_stb.storage, txstb, odomain="cxp_gtx_tx")
 
             word_count = Signal(max=100)
 
@@ -74,13 +180,13 @@ class Receiver(Module):
             # out fifo[97] IDLE IDLE fifo[99]
             # ack       1     0    0       1
             self.sync.cxp_gtx_tx += [
-            tx_fifo.source.ack.eq(0),
+                fifo_in.source.ack.eq(0),
 
                 If(word_count == 99,
                     word_count.eq(word_count.reset),
                 ).Else(
-                If(tx_fifo.source.stb & txstb,
+                    If(fifo_in.source.stb & txstb,
-                    If(word_count != 98, tx_fifo.source.ack.eq(1)),
+                        If(word_count != 98, fifo_in.source.ack.eq(1)),
                         word_count.eq(word_count + 1),
                     )
                 )
@@ -88,15 +194,15 @@ class Receiver(Module):
 
             # NOTE: prevent the first word send twice due to stream stb delay 
             self.comb += [
-            If((tx_fifo.source.stb & tx_fifo.source.ack & (word_count != 99)),
+                If((fifo_in.source.stb & fifo_in.source.ack & (word_count != 99)),
-                gtx.encoder.d[0].eq(tx_fifo.source.data[:8]),
+                    gtx.encoder.d[0].eq(fifo_in.source.data[:8]),
-                gtx.encoder.d[1].eq(tx_fifo.source.data[8:16]),
+                    gtx.encoder.d[1].eq(fifo_in.source.data[8:16]),
-                gtx.encoder.d[2].eq(tx_fifo.source.data[16:24]),
+                    gtx.encoder.d[2].eq(fifo_in.source.data[16:24]),
-                gtx.encoder.d[3].eq(tx_fifo.source.data[24:]),
+                    gtx.encoder.d[3].eq(fifo_in.source.data[24:]),
-                gtx.encoder.k[0].eq(tx_fifo.source.k[0]),
+                    gtx.encoder.k[0].eq(fifo_in.source.k[0]),
-                gtx.encoder.k[1].eq(tx_fifo.source.k[1]),
+                    gtx.encoder.k[1].eq(fifo_in.source.k[1]),
-                gtx.encoder.k[2].eq(tx_fifo.source.k[2]),
+                    gtx.encoder.k[2].eq(fifo_in.source.k[2]),
-                gtx.encoder.k[3].eq(tx_fifo.source.k[3]),
+                    gtx.encoder.k[3].eq(fifo_in.source.k[3]),
                 ).Else(
                     # NOTE: IDLE WORD
                     gtx.encoder.d[0].eq(0xBC),
@@ -110,6 +216,27 @@ class Receiver(Module):
                 )
             ]
 
+            # DEBUG: IO SMA & PMOD
+            if n == 0:
+                self.specials += [
+                    # Instance("OBUF", i_I=gtx.cd_cxp_gtx_rx.clk, o_O=debug_sma.p_tx),
+                    # Instance("OBUF", i_I=gtx.cd_cxp_gtx_tx.clk, o_O=debug_sma.n_rx),
+
+                    # # pmod 0-7 pin
+                    # Instance("OBUF", i_I=txstb, o_O=pmod_pads[0]),
+                    # Instance("OBUF", i_I=fifo_in.source.stb, o_O=pmod_pads[1]),
+                    # Instance("OBUF", i_I=fifo_in.source.ack, o_O=pmod_pads[2]),
+                    # Instance("OBUF", i_I=gtx.comma_checker.aligner_en, o_O=pmod_pads[3]),
+                    # Instance("OBUF", i_I=gtx.comma_checker.check_reset, o_O=pmod_pads[4]),
+                    # Instance("OBUF", i_I=gtx.comma_checker.has_comma, o_O=pmod_pads[5]),
+                    # Instance("OBUF", i_I=gtx.comma_checker.has_error, o_O=pmod_pads[6]),
+                    # Instance("OBUF", i_I=gtx.comma_checker.ready_sys, o_O=pmod_pads[7]),
+
+                    # Instance("OBUF", i_I=gtx.dclk, o_O=pmod_pads[0]),
+                    # Instance("OBUF", i_I=gtx.den, o_O=pmod_pads[1]),
+                    # Instance("OBUF", i_I=gtx.dwen, o_O=pmod_pads[2]),
+                    # Instance("OBUF", i_I=gtx.dready, o_O=pmod_pads[3]),
+                ]
 
 class QPLL(Module, AutoCSR):
     def __init__(self, refclk, sys_clk_freq):

src/gateware/cxp_pipeline.py

@@ -1,292 +1,296 @@
 from migen import *
 from misoc.interconnect.csr import *
 from misoc.interconnect import stream
+from misoc.cores.liteeth_mini.mac.crc import LiteEthMACCRCEngine, LiteEthMACCRCChecker
 
-char_width = 8
-char_layout = [("data", char_width), ("k", char_width//8)]
 
-word_dw = 32
+import struct
-word_layout = [("data", word_dw), ("k", word_dw//8)]
+
-buffer_depth = 128
+upconn_dw = 8
+upconn_layout = [("data", upconn_dw), ("k", upconn_dw//8)]
+
+downconn_dw = 32
+downconn_layout = [("data", downconn_dw), ("k", downconn_dw//8)]
+
 
 def K(x, y):
     return ((y << 5) | x)
 
 KCode = {
-    "pak_start" : C(K(27, 7), char_width),
+    "pak_start" : K(27, 7),
-    "io_ack" : C(K(28, 6), char_width), 
+    "io_ack" : K(28, 6), 
-    "trig_indic_28_2" : C(K(28, 2), char_width),
+    "trig_indic_28_2" : K(28, 2), 
-    "trig_indic_28_4" : C(K(28, 4), char_width),
+    "trig_indic_28_4" : K(28, 4), 
-    "pak_end" : C(K(29, 7), char_width),
+    "pak_end" : K(29, 7),
-    "idle_comma" : C(K(28, 5), char_width),
-    "idle_alignment" : C(K(28, 1), char_width),
 }
 
-class Packet_Wrapper(Module):
+
-    def __init__(self):
+def _bytes2word(bytes, big_endian=True):
-        self.sink = stream.Endpoint(word_layout)
+    if big_endian:
-        self.source = stream.Endpoint(word_layout)
+        return struct.unpack(">I", struct.pack(">4B", *bytes))[0]
+    else:
+        return struct.unpack("<I", struct.pack(">4B", *bytes))[0]
+
+class Code_Source(Module):
+    def __init__(self, layout, data, k):
+
+        self.source = stream.Endpoint(layout)
+        self.stb = Signal()
 
         # # #
+        assert len(data) == len(k) > 0
+        counts = len(data)
+
+        cnt = Signal() if counts == 1 else Signal(max=counts)
+        clr_cnt = Signal()
+        inc_cnt = Signal()
+
+        self.sync += [
+            If(clr_cnt,
+                cnt.eq(cnt.reset),
+            ).Elif(inc_cnt,
+                cnt.eq(cnt + 1),
+            )
+        ]
 
         self.submodules.fsm = fsm = FSM(reset_state="IDLE")
         
         fsm.act("IDLE",
-            self.sink.ack.eq(1),
+            clr_cnt.eq(1),
-            If(self.sink.stb,
+            If(self.stb,
-                self.sink.ack.eq(0),
+               NextState("WRITE")
-                NextState("INSERT_HEADER"),
             )
         )
 
-        fsm.act("INSERT_HEADER",
+        fsm.act("WRITE",
+            self.source.stb.eq(1),
+            self.source.data.eq(Array(data)[cnt]),
+            self.source.k.eq(Array(k)[cnt]),
+            If(cnt == counts - 1,
+                self.source.eop.eq(1),
+                If(self.source.ack, NextState("IDLE"))
+            ).Else(
+                inc_cnt.eq(self.source.ack)
+            )
+        )
+
+
+class Code_Inserter(Module):
+    def __init__(self, layout, data, k, insert_infront=True):
+        self.sink = stream.Endpoint(layout)
+        self.source = stream.Endpoint(layout)
+
+        self.data = Signal.like(self.sink.data)
+        self.k = Signal.like(self.sink.k)
+
+        # # #
+        assert len(data) == len(k) > 0
+        counts = len(data)
+
+        cnt = Signal() if counts == 1 else Signal(max=counts)
+        clr_cnt = Signal()
+        inc_cnt = Signal()
+
+        self.sync += [
+            If(clr_cnt,
+                cnt.eq(cnt.reset),
+            ).Elif(inc_cnt,
+                cnt.eq(cnt + 1),
+            )
+        ]
+
+        self.submodules.fsm = fsm = FSM(reset_state="IDLE")
+        remove_sink_oep = 0 if insert_infront else 1
+        
+        # add code in front: IDLE -> INSERT -> COPY
+        # add code at end: IDLE -> COPY -> INSERT
+        fsm.act("IDLE",
+            self.sink.ack.eq(1),
+            clr_cnt.eq(1),
+            If(self.sink.stb,
+                self.sink.ack.eq(0),
+                NextState("INSERT" if insert_infront else "COPY"),
+            )
+        )
+
+        fsm.act("INSERT",
             self.sink.ack.eq(0),
             self.source.stb.eq(1),
-            self.source.data.eq(Replicate(KCode["pak_start"], 4)),
+            self.source.data.eq(Array(data)[cnt]),
-            self.source.k.eq(0b1111),
+            self.source.k.eq(Array(k)[cnt]),
-            If(self.source.ack, NextState("COPY")),
+            If(cnt == counts - 1,
+                If(remove_sink_oep, self.source.eop.eq(1)),
+                If(self.source.ack, NextState("COPY" if insert_infront else "IDLE"))
+            ).Else(
+                inc_cnt.eq(self.source.ack)
+            )
         )
 
         fsm.act("COPY",
             self.sink.connect(self.source),
-            self.source.eop.eq(0),
+            If(remove_sink_oep, self.source.eop.eq(0)),
             If(self.sink.stb & self.sink.eop & self.source.ack,
-                NextState("INSERT_FOOTER"),
+                NextState("IDLE" if insert_infront else "INSERT"),
-            ),
+            )
         )
 
-        fsm.act("INSERT_FOOTER",
-            self.sink.ack.eq(0),
-            self.source.stb.eq(1),
-            self.source.data.eq(Replicate(KCode["pak_end"], 4)),
-            self.source.k.eq(0b1111),
-            self.source.eop.eq(1),
-            If(self.source.ack, NextState("IDLE")),
-        )
 
-class TX_Trigger(Module):
+class Packet_Wrapper(Module):
+    def __init__(self, layout):
+        self.submodules.pak_start = pak_start = Code_Inserter(layout, [KCode["pak_start"]]*4, [1]*4) 
+        self.submodules.pak_end = pak_end = Code_Inserter(layout, [KCode["pak_end"]]*4, [1]*4, insert_infront=False) 
+
+        self.comb += pak_start.source.connect(pak_end.sink),
+        self.sink = pak_start.sink
+        self.source = pak_end.source
+        
+@ResetInserter()
+@CEInserter()
+class CXPCRC32(Module):
+    # Section 9.2.2.2 (CXP-001-2021)
+    width = 32
+    polynom = 0x04C11DB7
+    seed = 2**width-1
+    check = 0x00000000
+    def __init__(self, data_width):
+        self.data = Signal(data_width)
+        self.value = Signal(self.width)
+        self.error = Signal()
+
+        # # #
+
+        self.submodules.engine = LiteEthMACCRCEngine(data_width, self.width, self.polynom)
+        reg = Signal(self.width, reset=self.seed)
+        self.sync += reg.eq(self.engine.next)
+        self.comb += [
+            self.engine.data.eq(self.data),
+            self.engine.last.eq(reg),
+
+            self.value.eq(reg[::-1]),
+            self.error.eq(self.engine.next != self.check)
+        ]
+
+class CXPCRC32Checker(LiteEthMACCRCChecker):
+    def __init__(self, layout):
+        LiteEthMACCRCChecker.__init__(self, CXPCRC32, layout)
+
+class TX_Trigger(Module, AutoCSR):
     def __init__(self):
-        self.stb = Signal()
+        self.trig_stb = Signal()
-        self.delay = Signal(char_width) 
+        self.delay = Signal(upconn_dw) 
         self.linktrig_mode = Signal(max=4)
 
         # # #
 
-        self.sink = stream.Endpoint(char_layout)
-        self.source = stream.Endpoint(char_layout)
-
         # Table 15 & 16 (CXP-001-2021)
         # Send [K28.2, K28.4, K28.4] or [K28.4, K28.2, K28.2] and 3x delay as trigger packet 
 
-        trig_packet = [Signal(char_width), Signal(char_width), Signal(char_width), self.delay, self.delay, self.delay]
+        self.submodules.code_src = code_src = Code_Source(upconn_layout, [self.delay]*3, [0]*3)
-        trig_packet_k = [1, 1, 1, 0, 0, 0]
+        self.comb += code_src.stb.eq(self.trig_stb),
-        self.comb += [
+
+        header = [Signal(8) for _ in range(3)]
+        self.comb += \
             If((self.linktrig_mode == 0) | (self.linktrig_mode == 2),
-                trig_packet[0].eq(KCode["trig_indic_28_2"]),
+                header[0].eq(KCode["trig_indic_28_2"]),
-                trig_packet[1].eq(KCode["trig_indic_28_4"]),
+                header[1].eq(KCode["trig_indic_28_4"]),
-                trig_packet[2].eq(KCode["trig_indic_28_4"]),
+                header[2].eq(KCode["trig_indic_28_4"]),
             ).Else(
-                trig_packet[0].eq(KCode["trig_indic_28_4"]),
+                header[0].eq(KCode["trig_indic_28_4"]),
-                trig_packet[1].eq(KCode["trig_indic_28_2"]),
+                header[1].eq(KCode["trig_indic_28_2"]),
-                trig_packet[2].eq(KCode["trig_indic_28_2"]),
+                header[2].eq(KCode["trig_indic_28_2"]),
-            ),
-        ]
-        
-        self.submodules.fsm = fsm = FSM(reset_state="COPY")
-        
-        cnt = Signal(max=6)
-        fsm.act("COPY",
-            NextValue(cnt, cnt.reset),
-            self.sink.connect(self.source),
-            If(self.stb, NextState("WRITE_TRIG"))
             )
         
-        fsm.act("WRITE_TRIG",
+        self.submodules.inserter = inserter = Code_Inserter(upconn_layout, header, [1]*3)
-            self.sink.ack.eq(0),
-            self.source.stb.eq(1),
-            self.source.data.eq(Array(trig_packet)[cnt]),
-            self.source.k.eq(Array(trig_packet_k)[cnt]),
-            If(self.source.ack,
-                If(cnt == 5,
-                    NextState("COPY"),
-                ).Else(
-                    NextValue(cnt, cnt + 1),
-                )
-            )
-        )
 
-class Idle_Word_Inserter(Module):
+        self.comb += code_src.source.connect(inserter.sink)
+        self.source = inserter.source
+
+class Trigger_ACK(Module):
     def __init__(self):
-        self.stb = Signal()
+        self.ack = Signal()
-
-        # # #
-
-        # Section 9.2.5 (CXP-001-2021)
-        # Send K28.5, K28.1, K28.1, D21.5  as idle word
-        self.submodules.fsm = fsm = FSM(reset_state="COPY")
-        
-        self.sink = stream.Endpoint(word_layout)
-        self.source = stream.Endpoint(word_layout)
-        fsm.act("COPY",
-            self.sink.connect(self.source),
-            If(self.stb, NextState("WRITE_IDLE"))
-        )
-
-        fsm.act("WRITE_IDLE",
-            self.sink.ack.eq(0),
-            self.source.stb.eq(1),
-            self.source.data.eq(Cat(KCode["idle_comma"], KCode["idle_alignment"], KCode["idle_alignment"], C(0xB5, char_width))),
-            self.source.k.eq(0b1110),
-            If(self.source.ack, NextState("COPY")),
-        )
-
-
-class Trigger_ACK_Inserter(Module):
-    def __init__(self):
-        self.stb = Signal()
 
         # # #
 
         # Section 9.3.2 (CXP-001-2021)
         # Send 4x K28.6 and 4x 0x01 as trigger packet ack
-        self.submodules.fsm = fsm = FSM(reset_state="COPY")
+        self.submodules.code_src = code_src = Code_Source(upconn_layout, [0x01]*4, [0]*4)
+        self.submodules.inserter = inserter = Code_Inserter(upconn_layout, [KCode["io_ack"]]*4, [1]*4)
+        self.comb += [
+            code_src.stb.eq(self.ack),
+            code_src.source.connect(inserter.sink)
+        ]
 
-        self.sink = stream.Endpoint(word_layout)
+        self.source = inserter.source
-        self.source = stream.Endpoint(word_layout)
-        fsm.act("COPY",
-            self.sink.connect(self.source),
-            If(self.stb, NextState("WRITE_ACK0"))
-        )
 
-        fsm.act("WRITE_ACK0",
-            self.sink.ack.eq(0),
-            self.source.stb.eq(1),
-            self.source.data.eq(Replicate(KCode["io_ack"], 4)),
-            self.source.k.eq(0b1111),
-            If(self.source.ack, NextState("WRITE_ACK1")),
-        )
-
-        fsm.act("WRITE_ACK1",
-            self.sink.ack.eq(0),
-            self.source.stb.eq(1),
-            self.source.data.eq(Replicate(C(0x01, char_width), 4)),
-            self.source.k.eq(0b0000),
-            If(self.source.ack, NextState("COPY")),
-        )
-
-
-@FullMemoryWE()
 class TX_Command_Packet(Module, AutoCSR):
-    def __init__(self):
+        # Section 12.1.2 (CXP-001-2021)
-        self.tx_word_len = CSRStorage(bits_for(buffer_depth))
+        # Max control packet size is 128 bytes
-        self.tx = CSR()
+    def __init__(self, fifo_depth=128):
+        self.len = CSRStorage(log2_int(fifo_depth))
+        self.data = CSR(upconn_dw)
+        self.writeable = CSRStatus()
 
         # # #
 
-        self.specials.mem = mem = Memory(word_dw, buffer_depth)
+        self.submodules.fifo = fifo = stream.SyncFIFO(upconn_layout, fifo_depth)
-        self.specials.mem_port = mem_port = mem.get_port()
+        self.submodules.pak_wrp = pak_wrp = Packet_Wrapper(upconn_layout)
-        self.source = stream.Endpoint(word_layout)
+        self.source = pak_wrp.source
 
+        self.comb += fifo.source.connect(pak_wrp.sink)
 
-        tx_done = Signal()
+        cnt = Signal(log2_int(fifo_depth), reset=1)
-        addr_next = Signal(bits_for(buffer_depth))
-        addr = Signal.like(addr_next)
-        addr_rst = Signal()
-        addr_inc = Signal()
-
-        # increment addr in the same cycle the moment addr_inc is high
-        # as memory takes one cycle to shift to the correct addr
         self.sync += [
-            addr.eq(addr_next),
+            self.writeable.status.eq(fifo.sink.ack),
-            If(self.tx.re, self.tx.w.eq(1)),
+            If(fifo.sink.ack, fifo.sink.stb.eq(0)),
-            If(tx_done, self.tx.w.eq(0)),
+            If(self.data.re,
-        ]
+                fifo.sink.stb.eq(1),
+                fifo.sink.data.eq(self.data.r),
 
-        self.comb += [
+                fifo.sink.k.eq(0),
-            addr_next.eq(addr),
+                If(cnt == self.len.storage,
-            If(addr_rst,
+                    fifo.sink.eop.eq(1),
-                addr_next.eq(addr_next.reset),
+                    cnt.eq(cnt.reset),
-            ).Elif(addr_inc,
+                ).Else(
-                addr_next.eq(addr + 1),
+                    fifo.sink.eop.eq(0),
+                    cnt.eq(cnt + 1),
                 ),
-            mem_port.adr.eq(addr_next),
+            )
-            self.source.data.eq(mem_port.dat_r)
         ]
 
-        self.submodules.fsm = fsm = FSM(reset_state="IDLE")
-
-        fsm.act("IDLE",
-            addr_rst.eq(1),
-            If(self.tx.re, NextState("TRANSMIT"))
-        )
-        fsm.act("TRANSMIT",
-            self.source.stb.eq(1),
-            If(self.source.ack,
-                addr_inc.eq(1),
-            ),
-            If(addr_next == self.tx_word_len.storage,
-                self.source.eop.eq(1),
-                tx_done.eq(1),
-                NextState("IDLE")
-            )
-        )
-
 class TX_Test_Packet(Module, AutoCSR):
     def __init__(self):
-        self.tx = CSR()
+
+        self.stb = CSR()
+        self.busy = CSRStatus()
 
         # # #
 
-        tx_done = Signal()
+        self.submodules.test_pattern_src = test_pattern_src = Code_Source(upconn_layout, [*range(0x100)]*16, [0]*0x100*16)
-        self.sync += [
+        self.submodules.pak_type_inserter = pak_type_inserter = Code_Inserter(upconn_layout, [0x04]*4, [0]*4)
-            If(self.tx.re, self.tx.w.eq(1)),
+        self.submodules.pak_wrp = pak_wrp = Packet_Wrapper(upconn_layout)
-            If(tx_done, self.tx.w.eq(0)),
+        self.comb += [
+            test_pattern_src.source.connect(pak_type_inserter.sink),
+            pak_type_inserter.source.connect(pak_wrp.sink),
         ]
 
-        self.source = stream.Endpoint(word_layout)
+        self.source = pak_wrp.source
-        self.submodules.fsm = fsm = FSM(reset_state="IDLE")
+        self.sync += [
-        
+            test_pattern_src.stb.eq(self.stb.re),
-        cnt = Signal(0xFFF)
+            If(self.stb.re,
-        fsm.act("IDLE",
+                self.busy.status.eq(1),
-            NextValue(cnt, cnt.reset),
+            ).Elif(self.source.eop & self.source.ack,
-            If(self.tx.re,
+                self.busy.status.eq(0)
-               NextState("WRITE_PACKET_TYPE")
             )
-        )
+        ]
-
-        fsm.act("WRITE_PACKET_TYPE",
-            self.source.stb.eq(1),
-            self.source.data.eq(Replicate(C(0x04, char_width), 4)),
-            self.source.k.eq(0b0000),
-            If(self.source.ack,NextState("WRITE_TEST_COUNTER"))
-        )
-
-        fsm.act("WRITE_TEST_COUNTER",
-            self.source.stb.eq(1),
-            self.source.data.eq(Cat(cnt[:8], cnt[:8]+1, cnt[:8]+2, cnt[:8]+3)),
-            self.source.k.eq(0b0000),
-            If(self.source.ack,
-                If(cnt == 0xFFF-3,
-                    tx_done.eq(1),
-                    self.source.eop.eq(1),
-                    NextState("IDLE")
-                ).Else(
-                    NextValue(cnt, cnt + 4),
-                )
-               
-            )
-        )
-
-
 
 class RX_Debug_Buffer(Module,AutoCSR):
     def __init__(self):
-        self.submodules.buf_out = buf_out = stream.SyncFIFO(word_layout, 128)
+        self.submodules.buf_out = buf_out = stream.SyncFIFO(downconn_layout, 128)
         self.sink = buf_out.sink
 
         self.inc = CSR()
-        self.dout_pak = CSRStatus(word_dw)
+        self.dout_pak = CSRStatus(downconn_dw)
-        self.kout_pak = CSRStatus(word_dw//8)
+        self.kout_pak = CSRStatus(downconn_dw//8)
         self.dout_valid = CSRStatus()
 
         self.sync += [
@@ -297,63 +301,110 @@ class RX_Debug_Buffer(Module,AutoCSR):
             self.dout_valid.status.eq(buf_out.source.stb),
         ]
 
-@FullMemoryWE()
+class Receiver_Path(Module, AutoCSR):
+    def __init__(self):
+        self.trig_ack = Signal()
+        self.trig_clr = Signal()
+
+        self.packet_type = Signal(8)
+        self.decoder_err = Signal()
+        self.decoder_err_clr = Signal()
+
+        self.test_err = Signal()
+        self.test_err_clr = Signal()
+
+        # # #
+
+        
+        self.submodules.trig_ack_checker = trig_ack_checker = CXP_Trig_Ack_Checker()
+        self.submodules.packet_decoder = packet_decoder = CXP_Data_Packet_Decode()
+
+        # Error are latched
+        self.sync += [
+            If(trig_ack_checker.ack,
+                self.trig_ack.eq(1),
+            ).Elif(self.trig_clr,
+                self.trig_ack.eq(0),
+            ),
+
+            If(packet_decoder.decode_err,
+                self.decoder_err.eq(1),
+            ).Elif(self.decoder_err_clr,
+                self.decoder_err.eq(0),
+            ),
+
+            If(packet_decoder.test_err,
+                self.test_err.eq(1),
+            ).Elif(self.test_err_clr,
+                self.test_err.eq(0),
+            )
+        ]
+        self.comb += [
+            self.packet_type.eq(packet_decoder.packet_type),
+            
+        ]
+
+        pipeline = [ trig_ack_checker, packet_decoder ]
+
+        for s, d in zip(pipeline, pipeline[1:]):
+            self.comb += s.source.connect(d.sink)
+
+        self.sink = pipeline[0].sink
+        self.source = pipeline[-1].source
+
+
+    
 class CXP_Data_Packet_Decode(Module):
     def __init__(self):
-        self.packet_type = Signal(8)
+        self.sink = stream.Endpoint(downconn_layout)
-        self.write_ptr = Signal(bits_for(buffer_depth))
+        # This is where data stream comes out
+        self.source = stream.Endpoint(downconn_layout)
 
-        self.new_packet = Signal()
+        self.packet_type = Signal(8)
         self.decode_err = Signal()
+
+        self.buffer = Signal(40*downconn_dw)
         self.test_err = Signal()
         # # #
 
-        # DEBUG: remove debug
+        # decoder -> priorities mux(normal packet vs trigger ack) -> data packet mux (control ack, data stream, heartbeat, testmode, (optional Genlcam event))
-        # TODO: decode all packet type here
-        # TODO: data&event -> memory
-        # TODO: heartbeat
         type = {
             "data_stream": 0x01,
             "control_ack_no_tag": 0x03,
             "test_packet": 0x04,
             "control_ack_with_tag": 0x06,
-            "event": 0x07,
+            "event_ack": 0x08,
             "heartbeat": 0x09,
 
             "debug" : 0x02,
         }
 
-        self.sink = stream.Endpoint(word_layout)
-        self.source = stream.Endpoint(word_layout)
-
         self.submodules.fsm = fsm = FSM(reset_state="IDLE")
 
         fsm.act("IDLE",
             self.sink.ack.eq(1),
             # TODO: add error correction?
-            If((self.sink.stb & (self.sink.data == Replicate(KCode["pak_start"], 4)) & (self.sink.k == 0b1111)),
+            If((self.sink.stb & (self.sink.data == _bytes2word([KCode["pak_start"]]*4)) & (self.sink.k == 0b1111)),
                 NextState("DECODE"),
             )
         )
 
+        # TODO: decode all packet type here
+
         cnt = Signal(max=0x100)
+
         fsm.act("DECODE",
             self.sink.ack.eq(1),
             If(self.sink.stb,
-                self.new_packet.eq(1),
                 NextValue(self.packet_type, self.sink.data[:8]),
 
                 Case(self.sink.data[:8],{
                     type["data_stream"]: NextState("STREAMING"),
-                    type["control_ack_no_tag"]: NextState("LOAD_BUFFER"),
+                    type["debug"]: NextState("STREAMING"),
                     type["test_packet"]: [
-                        NextValue(cnt, cnt.reset),
+                        NextValue(cnt, 0),
                         NextState("VERIFY_TEST_PATTERN"),
                     ],
-                    type["control_ack_with_tag"]: NextState("LOAD_BUFFER"),
-                    type["event"]: NextState("LOAD_BUFFER"),
-
-                    type["debug"]: NextState("LOAD_BUFFER"),
                     "default": [
                          self.decode_err.eq(1),
                          # wait till next valid packet
@@ -369,7 +420,7 @@ class CXP_Data_Packet_Decode(Module):
         fsm.act("VERIFY_TEST_PATTERN",
             self.sink.ack.eq(1),
             If(self.sink.stb,
-                If(((self.sink.data == Replicate(KCode["pak_end"], 4)) & (self.sink.k == 0b1111)),
+                If(((self.sink.data == _bytes2word([KCode["pak_end"]]*4)) & (self.sink.k == 0b1111)),
                     NextState("IDLE"),
                 ).Else(
                     If(((self.sink.data != Cat(cnt, cnt+1, cnt+2, cnt+3))),  
@@ -385,9 +436,8 @@ class CXP_Data_Packet_Decode(Module):
                 
         )
 
-        # For stream data packet
         fsm.act("STREAMING",
-            If((self.sink.stb & (self.sink.data == Replicate(KCode["pak_end"], 4)) & (self.sink.k == 0b1111)),
+            If((self.sink.stb & (self.sink.data == _bytes2word([KCode["pak_end"]]*4)) & (self.sink.k == 0b1111)),
                 # discard K29,7
                 self.sink.ack.eq(1),
                 NextState("IDLE")
@@ -395,41 +445,49 @@ class CXP_Data_Packet_Decode(Module):
                 self.sink.connect(self.source),
             )      
         )
+        # # input pipeline stage - determine packet length based on type
+        # self.sync += [
+        #     packet_start.eq((self.sink.data[0] == K(27, 7)) & (self.sink.k[0] == 1)),
+        #     packet_end.eq((self.sink.data[0] == K(29, 7)) & (self.sink.k[0] == 1)),
 
-        # A circular buffer for firmware to read packet from
+        #     If((self.sink.data[0] == K(27, 7)) & (self.sink.k[0] == 1),
-        self.specials.mem = mem = Memory(word_dw, buffer_depth)
+        #        packet_buffer_load.eq(1),
-        self.specials.mem_port = mem_port = mem.get_port(write_capable=True)
+        #     ),
 
-        self.comb += mem_port.adr.eq(self.write_ptr),
 
-        # For control ack, event packet
+        #     trig_ack.eq((self.sink.data[0] == K(28, 6)) & (self.sink.k[0] == 1)),
-        fsm.act("LOAD_BUFFER",
+        #     If(trig_ack,
-            mem_port.we.eq(0),
+        #         self.trig_ack.eq(self.sink.data[0]),
-            self.sink.ack.eq(1),
+        #         trig_ack.eq(0),
-            If(self.sink.stb,
+        #     ).Elif(packet_buffer_load,
-                If(((self.sink.data == Replicate(KCode["pak_end"], 4)) & (self.sink.k == 0b1111)),
+        #         # TODO: add test packet counting
-                    NextState("IDLE"),
+        #         Case(buffer_count,
-                ).Else(
+        #              {i: buffer[i*downconn_dw:(i+1)*downconn_dw].eq(self.sink.data)
-                    mem_port.we.eq(1),
+        #               for i in range(40)}),
-                    mem_port.dat_w.eq(self.sink.data),
+        #         buffer_count.eq(buffer_count + 1),
-                    NextValue(self.write_ptr, self.write_ptr + 1),
+
-                )
-            )
-        )
 
 class CXP_Trig_Ack_Checker(Module, AutoCSR):
     def __init__(self):
-        self.sink = stream.Endpoint(word_layout)
+        self.sink = stream.Endpoint(downconn_layout)
-        self.source = stream.Endpoint(word_layout)
+        self.source = stream.Endpoint(downconn_layout)
 
         self.ack = Signal()
 
         # # #
 
-        self.submodules.fsm = fsm = FSM(reset_state="COPY")
+        self.submodules.fsm = fsm = FSM(reset_state="IDLE")
+
+        fsm.act("IDLE",
+            self.sink.ack.eq(1),
+            If(self.sink.stb,
+                self.sink.ack.eq(0),
+                NextState("COPY"),
+            )
+        )
 
         fsm.act("COPY",
-            If((self.sink.stb & (self.sink.data == Replicate(KCode["io_ack"], 4)) & (self.sink.k == 0b1111)),
+            If((self.sink.stb & (self.sink.data == _bytes2word([KCode["io_ack"]]*4)) & (self.sink.k == 0b1111)),
                 # discard K28,6
                 self.sink.ack.eq(1),
                 NextState("CHECK_ACK")
@@ -440,10 +498,10 @@ class CXP_Trig_Ack_Checker(Module, AutoCSR):
 
         fsm.act("CHECK_ACK",
             If(self.sink.stb,
-                NextState("COPY"),
+                NextState("IDLE"),
                 # discard the word after K28,6
                 self.sink.ack.eq(1),
-                If(self.sink.data == Replicate(C(0x01, char_width), 4),
+                If(self.sink.data == _bytes2word([0x01]*4),
                     self.ack.eq(1),
                 )
             )

src/gateware/cxp_upconn.py

@@ -1,12 +1,21 @@
 from math import ceil
 
 from migen import *
+from migen.genlib.coding import PriorityEncoder
 
 from misoc.cores.code_8b10b import SingleEncoder
 from misoc.interconnect import stream
 from misoc.interconnect.csr import *
 
-from cxp_pipeline import char_layout
+from cxp_pipeline import upconn_layout
+
+IDLE_CHARS = Array([
+    #[char, k]
+    [0xBC, 1], #K28.5
+    [0x3C, 1], #K28.1
+    [0x3C, 1], #K28.1
+    [0xB5, 0], #D21.5
+])
 
 @ResetInserter()
 class UpConn_ClockGen(Module):
@@ -85,6 +94,173 @@ class SERDES_10bits(Module):
             )
         ]
 
+@ResetInserter()
+class Transmit_Scheduler(Module):
+    def __init__(self, interface, debug_buf):
+        self.tx_enable = Signal()
+
+        self.oe = Signal()
+        self.ce = Signal()
+
+        # # #
+
+        self.submodules.startup_fsm = startup_fsm = CEInserter()(FSM(reset_state="WAIT_TX_ENABLE"))
+        self.submodules.encoder = encoder = CEInserter()(SingleEncoder(True))
+        self.comb += [
+            startup_fsm.ce.eq(self.ce),
+            encoder.ce.eq(self.ce),
+        ]
+
+        tx_charcount = Signal(max=4)
+        tx_wordcount = Signal(max=10000)
+
+        idling = Signal()
+        priorities = Signal.like(interface.pe.o)
+
+        # DEBUG:
+        self.idling = Signal()
+        self.tx_charcount = Signal(max=4)
+        self.comb += [
+            self.idling.eq(idling),
+            self.tx_charcount.eq(tx_charcount),
+        ]
+
+        startup_fsm.act("WAIT_TX_ENABLE",
+            If(self.tx_enable,
+                NextValue(idling, 1),
+                NextValue(tx_charcount, 0),
+                NextValue(encoder.d, IDLE_CHARS[0][0]),
+                NextValue(encoder.k, IDLE_CHARS[0][1]),
+                NextState("START_TX"),
+
+                # DEBUG:
+                If(debug_buf.sink_ack,
+                    NextValue(debug_buf.sink_stb, 1),
+                    NextValue(debug_buf.sink_data, IDLE_CHARS[0][0]),
+                    NextValue(debug_buf.sink_k, IDLE_CHARS[0][1]),
+                )
+            )
+        )
+
+        startup_fsm.act("START_TX",
+            self.oe.eq(1),
+            If((~self.tx_enable) & (tx_charcount == 3),
+                NextState("WAIT_TX_ENABLE")
+            )
+        )
+
+        # hold ack for only one sys clk cycle to prevent data loss
+        for ack in interface.sink_ack:
+            self.sync += ack.eq(0)
+
+        self.sync += [
+            debug_buf.sink_stb.eq(0),
+            If(self.oe & self.ce,
+                encoder.disp_in.eq(encoder.disp_out),
+                If((~interface.pe.n) & (interface.pe.o == 0),
+                    # trigger packets are inserted at char boundary and don't contribute to word count
+                    interface.sink_ack[0].eq(1),
+                    encoder.d.eq(interface.sink_data[0]),
+                    encoder.k.eq(interface.sink_k[0]),
+
+                    # DEBUG:
+                    If(debug_buf.sink_ack,
+                        debug_buf.sink_stb.eq(1),
+                        debug_buf.sink_data.eq(interface.sink_data[0]),
+                        debug_buf.sink_k.eq(interface.sink_k[0]),
+                    )
+                ).Else(
+                    If(tx_charcount == 3,
+                        tx_charcount.eq(0),
+
+                        # Section 9.2.4 (CXP-001-2021)
+                        # other priorities packets are inserted at word boundary
+                        If((~interface.pe.n) & (tx_wordcount != 9999),
+                            idling.eq(0),
+                            priorities.eq(interface.pe.o),
+                            tx_wordcount.eq(tx_wordcount + 1),
+
+                            interface.sink_ack[interface.pe.o].eq(1),
+                            encoder.d.eq(interface.sink_data[interface.pe.o]),
+                            encoder.k.eq(interface.sink_k[interface.pe.o]),
+
+                            # DEBUG:
+                            If(debug_buf.sink_ack,
+                                debug_buf.sink_stb.eq(1),
+                                debug_buf.sink_data.eq(interface.sink_data[interface.pe.o]),
+                                debug_buf.sink_k.eq(interface.sink_k[interface.pe.o]),
+                            )
+                        ).Else(
+                            # Section 9.2.5.1 (CXP-001-2021)
+                            # IDLE word shall be transmitted at least once every 10,000 words, but should not be inserted into trigger packet
+                            idling.eq(1),
+                            tx_wordcount.eq(0),
+
+                            encoder.d.eq(IDLE_CHARS[0][0]),
+                            encoder.k.eq(IDLE_CHARS[0][1]),
+
+                            # DEBUG:
+                            If(debug_buf.sink_ack,
+                                debug_buf.sink_stb.eq(1),
+                                debug_buf.sink_data.eq(IDLE_CHARS[0][0]),
+                                debug_buf.sink_k.eq(IDLE_CHARS[0][1]),
+                            )
+                        )
+                    ).Else(
+                        tx_charcount.eq(tx_charcount + 1),
+                        If(~idling,
+                            tx_wordcount.eq(tx_wordcount + 1),
+                            interface.sink_ack[priorities].eq(1),
+                            encoder.d.eq(interface.sink_data[priorities]),
+                            encoder.k.eq(interface.sink_k[priorities]),
+
+                            # DEBUG:
+                            If(debug_buf.sink_ack,
+                                debug_buf.sink_stb.eq(1),
+                                debug_buf.sink_data.eq(interface.sink_data[priorities]),
+                                debug_buf.sink_k.eq(interface.sink_k[priorities]),
+                            )
+                        ).Else(
+                            encoder.d.eq(IDLE_CHARS[tx_charcount + 1][0]),
+                            encoder.k.eq(IDLE_CHARS[tx_charcount + 1][1]),
+
+                            # DEBUG:
+                            If(debug_buf.sink_ack,
+                                debug_buf.sink_stb.eq(1),
+                                debug_buf.sink_data.eq(IDLE_CHARS[tx_charcount + 1][0]),
+                                debug_buf.sink_k.eq(IDLE_CHARS[tx_charcount + 1][1]),
+                            )
+                        )
+                    ),       
+                ),
+            )
+        ]
+
+class PHY_Interface(Module):
+    def __init__(self, layout, nsink):
+        sink_stb = Signal(nsink)
+        self.sink_ack = Array(Signal() for _ in range(nsink))
+        self.sink_data = Array(Signal(8) for _ in range(nsink))
+        self.sink_k = Array(Signal() for _ in range(nsink))
+
+        # # #
+
+        self.sinks = []
+        for i in range(nsink):
+            sink = stream.Endpoint(layout)
+            self.sinks += [sink]
+
+            self.comb += [
+                sink.ack.eq(self.sink_ack[i]),
+                sink_stb[i].eq(sink.stb),
+                self.sink_data[i].eq(sink.data),
+                self.sink_k[i].eq(sink.k),
+            ]
+
+        # FIFOs transmission priority
+        self.submodules.pe = PriorityEncoder(nsink)
+        self.comb += self.pe.i.eq(sink_stb)
+
 class Debug_buffer(Module,AutoCSR):
     def __init__(self, layout):
         self.sink_stb = Signal()
@@ -94,7 +270,7 @@ class Debug_buffer(Module,AutoCSR):
 
         # # #
 
-        self.submodules.buf_out = buf_out = stream.SyncFIFO(layout, 512)
+        self.submodules.buf_out = buf_out = stream.SyncFIFO(layout, 128)
 
         self.sync += [
             buf_out.sink.stb.eq(self.sink_stb),
@@ -117,70 +293,63 @@ class Debug_buffer(Module,AutoCSR):
         ]
 
 
-class Transmitter(Module, AutoCSR):
+class CXP_UpConn_PHY(Module, AutoCSR):
-    def __init__(self, pad, sys_clk_freq, debug_sma, pmod_pads):
+    def __init__(self, pad, sys_clk_freq, debug_sma, pmod_pads, nsink=3):
         self.bitrate2x_enable = Signal()
         self.clk_reset = Signal()
+
         self.tx_enable = Signal()
+        self.tx_busy = Signal()
 
         # # #
 
-        self.sink = stream.Endpoint(char_layout)
-
         self.submodules.cg = cg = UpConn_ClockGen(sys_clk_freq)
-        self.submodules.encoder = encoder = SingleEncoder(True)
+        self.submodules.interface = interface = PHY_Interface(upconn_layout, nsink)
-        self.submodules.debug_buf = debug_buf = Debug_buffer(char_layout)
 
-        oe = Signal()
+        self.sinks = interface.sinks
-        self.sync += [
-            If(self.tx_enable,
-                self.sink.ack.eq(0),
 
         # DEBUG:
-                debug_buf.sink_stb.eq(0),
+        self.submodules.debug_buf = debug_buf = Debug_buffer(upconn_layout)
-
-                If(cg.clk,
-                    oe.eq(1),
-                    encoder.disp_in.eq(encoder.disp_out),
-                    self.sink.ack.eq(1),
-                    encoder.d.eq(self.sink.data),
-                    encoder.k.eq(self.sink.k),
-
-                    # DEBUG:
-                    If(debug_buf.sink_ack,
-                        debug_buf.sink_stb.eq(1),
-                        debug_buf.sink_data.eq(self.sink.data),
-                        debug_buf.sink_k.eq(self.sink.k),
-                    )
-                )
-            ).Else(
-                # DEBUG:
-                debug_buf.sink_stb.eq(0),
-
-                # no backpressure
-                self.sink.ack.eq(1),
-                oe.eq(0),
-            )
-        ]
 
+        self.submodules.scheduler = scheduler = Transmit_Scheduler(interface, debug_buf)
         self.submodules.serdes = serdes = SERDES_10bits(pad)
 
         self.comb += [
+            self.tx_busy.eq(~interface.pe.n),
+
             cg.reset.eq(self.clk_reset),
             cg.freq2x_enable.eq(self.bitrate2x_enable),
 
+            scheduler.reset.eq(self.clk_reset),
+            scheduler.ce.eq(cg.clk),
+            scheduler.tx_enable.eq(self.tx_enable),
+
             serdes.reset.eq(self.clk_reset),
             serdes.ce.eq(cg.clk_10x),
-            serdes.d.eq(encoder.output),
+            serdes.d.eq(scheduler.encoder.output),
-            serdes.oe.eq(oe),
+            serdes.oe.eq(scheduler.oe),
         ]
 
         # DEBUG: remove pads
        
+        prioity_0 = Signal()
+        word_bound = Signal()
+
+        p0 = Signal()
+        p3 = Signal()
+        self.comb += [
+           prioity_0.eq((~interface.pe.n) & (interface.pe.o == 0)),
+           word_bound.eq(scheduler.tx_charcount == 3),
+
+           # because of clk delay
+           p0.eq(scheduler.tx_charcount == 2),
+           p3.eq(scheduler.tx_charcount  == 1),
+
+        ] 
         self.specials += [
             # # debug sma
-            # Instance("OBUF", i_I=serdes.o, o_O=debug_sma.p_tx),
+            Instance("OBUF", i_I=serdes.o, o_O=debug_sma.p_tx),
-            # Instance("OBUF", i_I=cg.clk_10x, o_O=debug_sma.n_rx),
+            Instance("OBUF", i_I=cg.clk_10x, o_O=debug_sma.n_rx),
 
 
 
@@ -203,10 +372,3 @@ class Transmitter(Module, AutoCSR):
             # Instance("OBUF", i_I=p3, o_O=pmod_pads[7]),
         ]
 
-class CXP_UpConn_PHYS(Module, AutoCSR):
-    def __init__(self, pads, sys_clk_freq, debug_sma, pmod_pads):
-        self.tx_phys = []
-        for i, pad in enumerate(pads):
-            tx = Transmitter(pad, sys_clk_freq, debug_sma, pmod_pads)
-            self.tx_phys.append(tx)
-            setattr(self.submodules, "tx"+str(i), tx)

src/gateware/zc706.py

@@ -25,8 +25,7 @@ import analyzer
 import acpki
 import drtio_aux_controller
 import zynq_clocking
-import cxp_4r_fmc
+import cxp_4r_fmc, cxp
-import cxp
 from config import write_csr_file, write_mem_file, write_rustc_cfg_file
 
 class SMAClkinForward(Module):
@@ -683,74 +682,39 @@ class CXP_FMC():
 
         platform.add_extension(debug_sma)
         platform.add_extension(pmod1_33)
-        debug_sma_pad = platform.request("user_sma_clock_33") 
         pmod_pads = [platform.request("pmod1_33", i) for i in range(8)]
 
         clk_freq = 125e6
 
-        links = 1
+        gtx_pads = [platform.request("CXP_HS", i) for i in range(4)]
-        cxp_downconn_pads = [platform.request("CXP_HS", i) for i in range(links)]
-        cxp_upconn_pads = [platform.request("CXP_LS", i) for i in range(links)]
 
-
+        self.submodules.cxp = cxp.CXP(
-        self.submodules.cxp_phys = cxp_phys = cxp.CXP_PHYS(
             refclk=self.cdr_clk,
-            upconn_pads=cxp_upconn_pads,
+            downconn_pads=gtx_pads,
-            downconn_pads=cxp_downconn_pads,
+            upconn_pads=platform.request("CXP_LS", 0),
             sys_clk_freq=clk_freq,
-            debug_sma=debug_sma_pad,
+            debug_sma=platform.request("user_sma_clock_33"),
             pmod_pads = pmod_pads
         )
-        self.csr_devices.append("cxp_phys")
+        self.csr_devices.append("cxp")
 
+        # TODO: add memory for tx & rx CXP
+        memory_name = "cxp_tx"
+        mem_size = self.cxp.get_mem_size()
+        memory_address = self.axi2csr.register_port(self.cxp.get_tx_port(), mem_size)
+        self.add_memory_region(memory_name, self.mem_map["csr"] + memory_address, mem_size)
+        cxp_memory_group = [ memory_name ]
+        self.add_memory_group("cxp_mem", cxp_memory_group)
 
-        cxp_csr_group = []
-        cxp_tx_mem_group = []
-        cxp_rx_mem_group = []
-        cxp_loopback_mem_group = []
-        for i, (tx, rx) in enumerate(zip(cxp_phys.upconn.tx_phys, cxp_phys.downconn.rx_phys)):
-            cxp_name = "cxp" + str(i)
-
-            # TODO: cdr = ClockDomainsRenamer({"cxp_gtx_rx": "cxp_gtx_rx" + str(i)})
-            
-            cxp_interface = cxp.CXP_Interface(tx, rx, debug_sma_pad, pmod_pads)
-            setattr(self.submodules, cxp_name, cxp_interface )
-            self.csr_devices.append(cxp_name)
-            cxp_csr_group.append(cxp_name)
-            
-
-            mem_size = cxp_interface .get_mem_size()
-
-            tx_mem_name = "cxp_tx" + str(i) + "_mem"
-            memory_address = self.axi2csr.register_port(cxp_interface.get_tx_port(), mem_size)
-            self.add_memory_region(tx_mem_name, self.mem_map["csr"] + memory_address, mem_size)
-            cxp_tx_mem_group.append(tx_mem_name)
-
-            rx_mem_name = "cxp_rx" + str(i) + "_mem"
-            memory_address = self.axi2csr.register_port(cxp_interface.get_rx_port(), mem_size)
-            self.add_memory_region(rx_mem_name, self.mem_map["csr"] + memory_address, mem_size)
-            cxp_rx_mem_group.append(rx_mem_name)
-
-
-            # DEBUG loopback tx memory
-            loopback_mem_name = "cxp_loopback_tx" + str(i) + "_mem"
-            cxp_loopback_mem_group.append(loopback_mem_name)
-            memory_address = self.axi2csr.register_port(cxp_interface.get_loopback_tx_port(), mem_size)
-            self.add_memory_region(loopback_mem_name, self.mem_map["csr"] + memory_address, mem_size)
-
-        self.add_memory_group("cxp_tx_mem", cxp_tx_mem_group)
-        self.add_memory_group("cxp_rx_mem", cxp_rx_mem_group)
-        self.add_memory_group("cxp_loopback_mem", cxp_loopback_mem_group)
-        self.add_csr_group("cxp", cxp_csr_group)
 
         # max freq of cxp_gtx_rx = linerate/internal_datawidth = 12.5Gbps/40 = 312.5MHz
         # zc706 use speed grade 2 which only support up to 10.3125Gbps (4ns)
         # pushing to 12.5Gbps (3.2ns) will result in Pulse width violation but setup/hold times are met
-        for rx in cxp_phys.downconn.rx_phys :
+        for gtx in self.cxp.downconn.gtxs:
-            platform.add_period_constraint(rx.gtx.cd_cxp_gtx_tx.clk, 3.2)
+            platform.add_period_constraint(gtx.cd_cxp_gtx_tx.clk, 3.2)
-            platform.add_period_constraint(rx.gtx.cd_cxp_gtx_rx.clk, 3.2)
+            platform.add_period_constraint(gtx.cd_cxp_gtx_rx.clk, 3.2)
             # constraint the CLK path 
-            platform.add_false_path_constraints(self.sys_crg.cd_sys.clk, rx.gtx.cd_cxp_gtx_tx.clk, rx.gtx.cd_cxp_gtx_rx.clk)
+            platform.add_false_path_constraints(self.sys_crg.cd_sys.clk, gtx.cd_cxp_gtx_tx.clk, gtx.cd_cxp_gtx_rx.clk)
 
         rtio_channels = []
         # FIXME remove this placeholder RTIO channel

src/libboard_artiq/src/cxp_downconn.rs

@@ -3,8 +3,7 @@ use libboard_zynq::{println, timer::GlobalTimer};
 use log::info;
 
 // use log::info;
-use crate::{cxp_proto,
+use crate::{cxp_proto, pl::csr};
-            pl::{csr, csr::CXP}};
 
 #[derive(Clone, Copy, Debug)]
 #[allow(non_camel_case_types)]
@@ -18,62 +17,64 @@ pub enum CXP_SPEED {
     CXP_12,
 }
 
-pub fn loopback_testing(channel: usize, timer: &mut GlobalTimer, speed: CXP_SPEED) {
+pub fn loopback_testing(timer: &mut GlobalTimer, speed: CXP_SPEED) {
     println!("==============================================================================");
-    cxp_gtx::change_linerate(channel, timer, speed);
+    cxp_gtx::change_linerate(timer, speed);
 
     unsafe {
         info!("waiting for tx&rx setup...");
         timer.delay_us(50_000);
         info!(
             "tx_phaligndone = {} | rx_phaligndone = {}",
-            (CXP[channel].downconn_txinit_phaligndone_read)(),
+            csr::cxp::downconn_phy_txinit_phaligndone_read(),
-            (CXP[channel].downconn_rxinit_phaligndone_read)(),
+            csr::cxp::downconn_phy_rxinit_phaligndone_read(),
         );
 
         // enable txdata tranmission thought MGTXTXP, required by PMA loopback
-        (CXP[channel].downconn_txenable_write)(1);
+        csr::cxp::downconn_phy_txenable_write(1);
 
         info!("waiting for rx to align...");
-        while (CXP[channel].downconn_rx_ready_read)() != 1 {}
+        while csr::cxp::downconn_phy_rx_ready_read() != 1 {}
         info!("rx ready!");
 
-        (CXP[channel].downconn_tx_stb_write)(1);
+        csr::cxp::downconn_phy_tx_stb_write(1);
-        cxp_proto::downconn_send_test_packet(channel);
+        cxp_proto::downconn_send_test_packet();
+        timer.delay_us(20000); // wait packet has arrive at rx
+        csr::cxp::downconn_phy_tx_stb_write(0);
 
-        cxp_proto::downconn_debug_send_trig_ack(channel);
+        // cxp_proto::downconn_debug_send_trig_ack();
 
-        cxp_proto::downconn_debug_send(
+        cxp_proto::downconn_debug_send(&cxp_proto::Packet::CtrlRead {
-            channel,
-            &cxp_proto::Packet::CtrlRead {
             addr: 0x00,
             length: 0x04,
-            },
+        });
-        )
-        .expect("loopback gtx tx error");
 
-        timer.delay_us(200); // wait packet has arrive at RX async fifo
+        timer.delay_us(200); // wait packet has arrive at async fifo in
-        (CXP[channel].downconn_tx_stb_write)(0);
+        csr::cxp::downconn_phy_tx_stb_write(1);
+        timer.delay_us(200);
+        csr::cxp::downconn_phy_tx_stb_write(0);
 
-        info!("trig ack = {}", (CXP[channel].downconn_trigger_ack_read)());
+        info!("trig ack = {}", csr::cxp::downconn_trig_ack_read());
-        (CXP[channel].downconn_trigger_ack_write)(1);
+        csr::cxp::downconn_trig_clr_write(1);
-        info!("after clr trig ack = {}", (CXP[channel].downconn_trigger_ack_read)());
+        info!("after clr trig ack = {}", csr::cxp::downconn_trig_ack_read());
 
-        info!("decoder error = {}", (CXP[channel].downconn_decoder_error_read)());
+        info!("decoder error = {}", csr::cxp::downconn_decoder_error_read());
-        info!("test error = {}", (CXP[channel].downconn_test_error_read)());
+        info!("test error = {}", csr::cxp::downconn_test_error_read());
-        info!("packet type = {:#06X}", (CXP[channel].downconn_packet_type_read)());
+        info!("packet type = {:#06X}", csr::cxp::downconn_packet_type_read());
+
+        // TODO: investigate how to make my packet appear
+        // TODO: discard idle word
 
-        cxp_proto::receive(channel);
         // DEBUG: print loopback packets
         const LEN: usize = 20;
         let mut pak_arr: [u32; LEN] = [0; LEN];
         let mut k_arr: [u8; LEN] = [0; LEN];
         let mut i: usize = 0;
-        while (CXP[channel].downconn_debug_out_dout_valid_read)() == 1 {
+        while csr::cxp::downconn_debug_out_dout_valid_read() == 1 {
-            pak_arr[i] = (CXP[channel].downconn_debug_out_dout_pak_read)();
+            pak_arr[i] = csr::cxp::downconn_debug_out_dout_pak_read();
-            k_arr[i] = (CXP[channel].downconn_debug_out_kout_pak_read)();
+            k_arr[i] = csr::cxp::downconn_debug_out_kout_pak_read();
             // println!("received {:#04X}", pak_arr[i]);
-            (CXP[channel].downconn_debug_out_inc_write)(1);
+            csr::cxp::downconn_debug_out_inc_write(1);
             i += 1;
             if i == LEN {
                 break;
@@ -84,69 +85,67 @@ pub fn loopback_testing(channel: usize, timer: &mut GlobalTimer, speed: CXP_SPEE
 }
 
 pub fn setup(timer: &mut GlobalTimer) {
-    // TODO: do a for loop for channel?
-    let channel: usize = 0;
     unsafe {
         info!("turning on pmc loopback mode...");
-        (CXP[channel].downconn_loopback_mode_write)(0b010); // Near-End PMA Loopback
+        csr::cxp::downconn_phy_loopback_mode_write(0b010); // Near-End PMA Loopback
 
         // QPLL setup
-        csr::cxp_phys::downconn_qpll_reset_write(1);
+        csr::cxp::downconn_phy_qpll_reset_write(1);
         info!("waiting for QPLL/CPLL to lock...");
-        while csr::cxp_phys::downconn_qpll_locked_read() != 1 {}
+        while csr::cxp::downconn_phy_qpll_locked_read() != 1 {}
         info!("QPLL locked");
 
         // tx/rx setup
-        (CXP[channel].downconn_tx_start_init_write)(1);
+        csr::cxp::downconn_phy_tx_start_init_write(1);
-        (CXP[channel].downconn_rx_start_init_write)(1);
+        csr::cxp::downconn_phy_rx_start_init_write(1);
 
         info!("waiting for tx & rx setup...");
         timer.delay_us(50_000);
         info!(
             "tx_phaligndone = {} | rx_phaligndone = {}",
-            (CXP[channel].downconn_txinit_phaligndone_read)(),
+            csr::cxp::downconn_phy_txinit_phaligndone_read(),
-            (CXP[channel].downconn_rxinit_phaligndone_read)(),
+            csr::cxp::downconn_phy_rxinit_phaligndone_read(),
         );
     }
 
-    cxp_gtx::change_linerate(channel, timer, CXP_SPEED::CXP_1);
+    cxp_gtx::change_linerate(timer, CXP_SPEED::CXP_1);
 }
 
 pub mod cxp_gtx {
     use super::*;
 
     struct CdrConfig {
-        pub cfg_reg0: u16, // addr = 0xA8
+        pub cfg_reg0: u16, //0x0A8
-        pub cfg_reg1: u16, // addr = 0xA9
+        pub cfg_reg1: u16, //0x0A9
-        pub cfg_reg2: u16, // addr = 0xAA
+        pub cfg_reg2: u16, //0x0AA
-        pub cfg_reg3: u16, // addr = 0xAB
+        pub cfg_reg3: u16, //0x0AB
-        pub cfg_reg4: u16, // addr = 0xAC
+        pub cfg_reg4: u16, //0x0AC
     }
 
-    pub fn change_linerate(channel: usize, timer: &mut GlobalTimer, speed: CXP_SPEED) {
+    pub fn change_linerate(timer: &mut GlobalTimer, speed: CXP_SPEED) {
         info!("Changing datarate to {:?}", speed);
         // DEBUG: DRP pll for TXUSRCLK = freq(linerate)/20
         let settings = txusrclk::get_txusrclk_config(speed);
-        txusrclk::setup(channel, timer, settings);
+        txusrclk::setup(timer, settings);
 
-        change_qpll_fb_divider(speed);
+        change_qpll_settings(speed);
-        change_gtx_divider(channel, speed);
+        change_cdr_cfg(speed);
-        change_cdr_cfg(channel, speed);
 
         unsafe {
-            csr::cxp_phys::downconn_qpll_reset_write(1);
+            csr::cxp::downconn_phy_qpll_reset_write(1);
             info!("waiting for QPLL/CPLL to lock...");
-            while csr::cxp_phys::downconn_qpll_locked_read() != 1 {}
+            while csr::cxp::downconn_phy_qpll_locked_read() != 1 {}
             info!("QPLL locked");
         }
 
         unsafe {
-            (CXP[channel].downconn_tx_restart_write)(1);
+            csr::cxp::downconn_phy_tx_restart_write(1);
-            (CXP[channel].downconn_rx_restart_write)(1);
+            csr::cxp::downconn_phy_rx_restart_write(1);
         }
     }
 
-    fn change_qpll_fb_divider(speed: CXP_SPEED) {
+    fn change_qpll_settings(speed: CXP_SPEED) {
+        // Change QPLL_FBDIV
         let qpll_div_reg = match speed {
             CXP_SPEED::CXP_1 | CXP_SPEED::CXP_2 | CXP_SPEED::CXP_5 | CXP_SPEED::CXP_10 => 0x0120, // FB_Divider = 80
             CXP_SPEED::CXP_3 | CXP_SPEED::CXP_6 | CXP_SPEED::CXP_12 => 0x0170,                    // FB_Divider = 100
@@ -155,24 +154,24 @@ pub mod cxp_gtx {
         println!("0x36 = {:#06x}", qpll_read(0x36));
         qpll_write(0x36, qpll_div_reg);
         println!("0x36 = {:#06x}", qpll_read(0x36));
-    }
 
-    fn change_gtx_divider(channel: usize, speed: CXP_SPEED) {
+        // DEBUG: remove txoutdiv
-        let div_reg = match speed {
+        let txrxout_div = match speed {
-            CXP_SPEED::CXP_1 => 0x33,                      // RXOUT_DIV = 8
+            CXP_SPEED::CXP_1 => 0x33,                      // 8
-            CXP_SPEED::CXP_2 | CXP_SPEED::CXP_3 => 0x22,   // RXOUT_DIV = 4
+            CXP_SPEED::CXP_2 | CXP_SPEED::CXP_3 => 0x22,   // 4
-            CXP_SPEED::CXP_5 | CXP_SPEED::CXP_6 => 0x11,   // RXOUT_DIV = 2
+            CXP_SPEED::CXP_5 | CXP_SPEED::CXP_6 => 0x11,   // 2
-            CXP_SPEED::CXP_10 | CXP_SPEED::CXP_12 => 0x00, // RXOUT_DIV = 1
+            CXP_SPEED::CXP_10 | CXP_SPEED::CXP_12 => 0x00, // 1
         };
 
-        println!("0x88 = {:#06x}", gtx_read(channel, 0x88));
+        // OUT_DIV
-        gtx_write(channel, 0x88, div_reg);
+        println!("0x88 = {:#06x}", gtx_read(0x88));
-        println!("0x88 = {:#06x}", gtx_read(channel, 0x88));
+        gtx_write(0x88, txrxout_div);
+        println!("0x88 = {:#06x}", gtx_read(0x88));
     }
 
-    fn change_cdr_cfg(channel: usize, speed: CXP_SPEED) {
+    fn change_cdr_cfg(speed: CXP_SPEED) {
         let cdr_cfg = match speed {
-            // when RXOUT_DIV = 8
+            // rxout_div = 8
             CXP_SPEED::CXP_1 => {
                 CdrConfig {
                     cfg_reg0: 0x0020, //0x0A8
@@ -182,7 +181,7 @@ pub mod cxp_gtx {
                     cfg_reg4: 0x0003, //0x0AC
                 }
             }
-            // when RXOUT_DIV = 4
+            // rxout_div = 4
             CXP_SPEED::CXP_2 | CXP_SPEED::CXP_5 => {
                 CdrConfig {
                     cfg_reg0: 0x0020, //0x0A8
@@ -192,7 +191,7 @@ pub mod cxp_gtx {
                     cfg_reg4: 0x0003, //0x0AC
                 }
             }
-            // when RXOUT_DIV= 2
+            // rxout_div = 2
             CXP_SPEED::CXP_3 | CXP_SPEED::CXP_6 => {
                 CdrConfig {
                     cfg_reg0: 0x0020, //0x0A8
@@ -202,7 +201,7 @@ pub mod cxp_gtx {
                     cfg_reg4: 0x0003, //0x0AC
                 }
             }
-            // when RXOUT_DIV= 1
+            // rxout_div = 1
             CXP_SPEED::CXP_10 | CXP_SPEED::CXP_12 => {
                 CdrConfig {
                     cfg_reg0: 0x0020, //0x0A8
@@ -214,48 +213,50 @@ pub mod cxp_gtx {
             }
         };
 
-        gtx_write(channel, 0x0A8, cdr_cfg.cfg_reg0);
+        gtx_write(0x0A8, cdr_cfg.cfg_reg0);
-        gtx_write(channel, 0x0A9, cdr_cfg.cfg_reg1);
+        gtx_write(0x0A9, cdr_cfg.cfg_reg1);
-        gtx_write(channel, 0x0AA, cdr_cfg.cfg_reg2);
+        gtx_write(0x0AA, cdr_cfg.cfg_reg2);
-        gtx_write(channel, 0x0AB, cdr_cfg.cfg_reg3);
+        gtx_write(0x0AB, cdr_cfg.cfg_reg3);
-        gtx_write(channel, 0x0AC, cdr_cfg.cfg_reg4);
+        gtx_write(0x0AC, cdr_cfg.cfg_reg4);
     }
 
     #[allow(dead_code)]
-    fn gtx_read(channel: usize, address: u16) -> u16 {
+    fn gtx_read(address: u16) -> u16 {
+        // DEBUG:
         unsafe {
-            (CXP[channel].downconn_gtx_daddr_write)(address);
+            csr::cxp::downconn_phy_gtx_daddr_write(address);
-            (CXP[channel].downconn_gtx_dread_write)(1);
+            csr::cxp::downconn_phy_gtx_dread_write(1);
-            while (CXP[channel].downconn_gtx_dready_read)() != 1 {}
+            while csr::cxp::downconn_phy_gtx_dready_read() != 1 {}
-            (CXP[channel].downconn_gtx_dout_read)()
+            csr::cxp::downconn_phy_gtx_dout_read()
         }
     }
 
-    fn gtx_write(channel: usize, address: u16, value: u16) {
+    fn gtx_write(address: u16, value: u16) {
         unsafe {
-            (CXP[channel].downconn_gtx_daddr_write)(address);
+            csr::cxp::downconn_phy_gtx_daddr_write(address);
-            (CXP[channel].downconn_gtx_din_write)(value);
+            csr::cxp::downconn_phy_gtx_din_write(value);
-            (CXP[channel].downconn_gtx_din_stb_write)(1);
+            csr::cxp::downconn_phy_gtx_din_stb_write(1);
-            while (CXP[channel].downconn_gtx_dready_read)() != 1 {}
+            while csr::cxp::downconn_phy_gtx_dready_read() != 1 {}
         }
     }
 
     #[allow(dead_code)]
     fn qpll_read(address: u8) -> u16 {
+        // DEBUG:
         unsafe {
-            csr::cxp_phys::downconn_qpll_daddr_write(address);
+            csr::cxp::downconn_phy_qpll_daddr_write(address);
-            csr::cxp_phys::downconn_qpll_dread_write(1);
+            csr::cxp::downconn_phy_qpll_dread_write(1);
-            while csr::cxp_phys::downconn_qpll_dready_read() != 1 {}
+            while csr::cxp::downconn_phy_qpll_dready_read() != 1 {}
-            csr::cxp_phys::downconn_qpll_dout_read()
+            csr::cxp::downconn_phy_qpll_dout_read()
         }
     }
 
     fn qpll_write(address: u8, value: u16) {
         unsafe {
-            csr::cxp_phys::downconn_qpll_daddr_write(address);
+            csr::cxp::downconn_phy_qpll_daddr_write(address);
-            csr::cxp_phys::downconn_qpll_din_write(value);
+            csr::cxp::downconn_phy_qpll_din_write(value);
-            csr::cxp_phys::downconn_qpll_din_stb_write(1);
+            csr::cxp::downconn_phy_qpll_din_stb_write(1);
-            while csr::cxp_phys::downconn_qpll_dready_read() != 1 {}
+            while csr::cxp::downconn_phy_qpll_dready_read() != 1 {}
         }
     }
 }
@@ -277,119 +278,119 @@ pub mod txusrclk {
         pub filt_reg2: u16,     //0x4F
     }
 
-    fn one_clock_cycle(channel: usize) {
+    fn one_clock_cycle() {
         unsafe {
-            (CXP[channel].downconn_pll_dclk_write)(1);
+            csr::cxp::downconn_phy_pll_dclk_write(1);
-            (CXP[channel].downconn_pll_dclk_write)(0);
+            csr::cxp::downconn_phy_pll_dclk_write(0);
         }
     }
 
-    fn set_addr(channel: usize, address: u8) {
+    fn set_addr(address: u8) {
         unsafe {
-            (CXP[channel].downconn_pll_daddr_write)(address);
+            csr::cxp::downconn_phy_pll_daddr_write(address);
         }
     }
 
-    fn set_data(channel: usize, value: u16) {
+    fn set_data(value: u16) {
         unsafe {
-            (CXP[channel].downconn_pll_din_write)(value);
+            csr::cxp::downconn_phy_pll_din_write(value);
         }
     }
 
-    fn set_enable(channel: usize, en: bool) {
+    fn set_enable(en: bool) {
         unsafe {
             let val = if en { 1 } else { 0 };
-            (CXP[channel].downconn_pll_den_write)(val);
+            csr::cxp::downconn_phy_pll_den_write(val);
         }
     }
 
-    fn set_write_enable(channel: usize, en: bool) {
+    fn set_write_enable(en: bool) {
         unsafe {
             let val = if en { 1 } else { 0 };
-            (CXP[channel].downconn_pll_dwen_write)(val);
+            csr::cxp::downconn_phy_pll_dwen_write(val);
         }
     }
 
-    fn get_data(channel: usize) -> u16 {
+    fn get_data() -> u16 {
-        unsafe { (CXP[channel].downconn_pll_dout_read)() }
+        unsafe { csr::cxp::downconn_phy_pll_dout_read() }
     }
 
-    fn drp_ready(channel: usize) -> bool {
+    fn drp_ready() -> bool {
-        unsafe { (CXP[channel].downconn_pll_dready_read)() == 1 }
+        unsafe { csr::cxp::downconn_phy_pll_dready_read() == 1 }
     }
 
     #[allow(dead_code)]
-    fn read(channel: usize, address: u8) -> u16 {
+    fn read(address: u8) -> u16 {
-        set_addr(channel, address);
+        set_addr(address);
-        set_enable(channel, true);
+        set_enable(true);
         // Set DADDR on the mmcm and assert DEN for one clock cycle
-        one_clock_cycle(channel);
+        one_clock_cycle();
 
-        set_enable(channel, false);
+        set_enable(false);
-        while !drp_ready(channel) {
+        while !drp_ready() {
             // keep the clock signal until data is ready
-            one_clock_cycle(channel);
+            one_clock_cycle();
         }
-        get_data(channel)
+        get_data()
     }
 
-    fn write(channel: usize, address: u8, value: u16) {
+    fn write(address: u8, value: u16) {
-        set_addr(channel, address);
+        set_addr(address);
-        set_data(channel, value);
+        set_data(value);
-        set_write_enable(channel, true);
+        set_write_enable(true);
-        set_enable(channel, true);
+        set_enable(true);
         // Set DADDR, DI on the mmcm and assert DWE, DEN for one clock cycle
-        one_clock_cycle(channel);
+        one_clock_cycle();
 
-        set_write_enable(channel, false);
+        set_write_enable(false);
-        set_enable(channel, false);
+        set_enable(false);
-        while !drp_ready(channel) {
+        while !drp_ready() {
             // keep the clock signal until write is finished
-            one_clock_cycle(channel);
+            one_clock_cycle();
         }
     }
 
-    fn reset(channel: usize, rst: bool) {
+    fn reset(rst: bool) {
         unsafe {
             let val = if rst { 1 } else { 0 };
-            (CXP[channel].downconn_txpll_reset_write)(val)
+            csr::cxp::downconn_phy_txpll_reset_write(val)
         }
     }
 
-    pub fn setup(channel: usize, timer: &mut GlobalTimer, settings: PLLSetting) {
+    pub fn setup(timer: &mut GlobalTimer, settings: PLLSetting) {
         if false {
-            info!("0x08 = {:#06x}", read(channel, 0x08));
+            info!("0x08 = {:#06x}", read(0x08));
-            info!("0x09 = {:#06x}", read(channel, 0x09));
+            info!("0x09 = {:#06x}", read(0x09));
-            info!("0x14 = {:#06x}", read(channel, 0x14));
+            info!("0x14 = {:#06x}", read(0x14));
-            info!("0x15 = {:#06x}", read(channel, 0x15));
+            info!("0x15 = {:#06x}", read(0x15));
-            info!("0x16 = {:#06x}", read(channel, 0x16));
+            info!("0x16 = {:#06x}", read(0x16));
-            info!("0x18 = {:#06x}", read(channel, 0x18));
+            info!("0x18 = {:#06x}", read(0x18));
-            info!("0x19 = {:#06x}", read(channel, 0x19));
+            info!("0x19 = {:#06x}", read(0x19));
-            info!("0x1A = {:#06x}", read(channel, 0x1A));
+            info!("0x1A = {:#06x}", read(0x1A));
-            info!("0x28 = {:#06x}", read(channel, 0x28));
+            info!("0x28 = {:#06x}", read(0x28));
-            info!("0x4E = {:#06x}", read(channel, 0x4E));
+            info!("0x4E = {:#06x}", read(0x4E));
-            info!("0x4F = {:#06x}", read(channel, 0x4F));
+            info!("0x4F = {:#06x}", read(0x4F));
         } else {
             // Based on "DRP State Machine" from XAPP888
             // hold reset HIGH during pll config
-            reset(channel, true);
+            reset(true);
-            write(channel, 0x08, settings.clkout0_reg1);
+            write(0x08, settings.clkout0_reg1);
-            write(channel, 0x09, settings.clkout0_reg2);
+            write(0x09, settings.clkout0_reg2);
-            write(channel, 0x14, settings.clkfbout_reg1);
+            write(0x14, settings.clkfbout_reg1);
-            write(channel, 0x15, settings.clkfbout_reg2);
+            write(0x15, settings.clkfbout_reg2);
-            write(channel, 0x16, settings.div_reg);
+            write(0x16, settings.div_reg);
-            write(channel, 0x18, settings.lock_reg1);
+            write(0x18, settings.lock_reg1);
-            write(channel, 0x19, settings.lock_reg2);
+            write(0x19, settings.lock_reg2);
-            write(channel, 0x1A, settings.lock_reg3);
+            write(0x1A, settings.lock_reg3);
-            write(channel, 0x28, settings.power_reg);
+            write(0x28, settings.power_reg);
-            write(channel, 0x4E, settings.filt_reg1);
+            write(0x4E, settings.filt_reg1);
-            write(channel, 0x4F, settings.filt_reg2);
+            write(0x4F, settings.filt_reg2);
-            reset(channel, false);
+            reset(false);
 
             // wait for the pll to lock
             timer.delay_us(100);
 
-            let locked = unsafe { (CXP[channel].downconn_txpll_locked_read)() == 1 };
+            let locked = unsafe { csr::cxp::downconn_phy_txpll_locked_read() == 1 };
             info!("txusrclk locked = {}", locked);
         }
     }
@@ -518,3 +519,5 @@ pub mod txusrclk {
         }
     }
 }
+
+// TODO: add recv like in drtioaux

src/libboard_artiq/src/cxp_proto.rs

@@ -2,22 +2,19 @@ use core::slice;
 
 use core_io::{Error as IoError, Write};
 use crc::crc32;
+use embedded_hal::prelude::_embedded_hal_blocking_delay_DelayUs;
 use io::Cursor;
-use libboard_zynq::println;
+use libboard_zynq::{println, timer::GlobalTimer};
 
-// TODO: fix the import
+use crate::{mem::mem::CXP_MEM, pl::csr};
-use crate::{mem::mem::{CXP_LOOPBACK_MEM, CXP_RX_MEM, CXP_TX_MEM},
-            pl::csr::CXP};
 
 const MAX_PACKET: usize = 128;
 const DATA_MAXSIZE: usize = /*max size*/MAX_PACKET - /*Tag*/4 - /*Op code & length*/4 - /*addr*/4 - /*CRC*/4 ;
-const MEM_LEN: usize = 0x200;
 
 #[derive(Debug)]
 pub enum Error {
     BufferError,
     LinkDown,
-    UnknownPacket(u8),
 }
 
 impl From<IoError> for Error {
@@ -110,89 +107,71 @@ impl Packet {
     }
 }
 
-pub fn receive(channel: usize) -> Result<(), Error> {
+pub fn send(packet: &Packet) -> Result<(), Error> {
-    unsafe {
+    if unsafe { csr::cxp::upconn_tx_enable_read() } == 0 {
-        // let ptr = CXP_LOOPBACK_MEM[0].base as *mut u32;
-        let ptr = CXP_RX_MEM[0].base as *mut u32;
-        // let mut reader = Cursor::new(slice::from_raw_parts_mut(ptr as *mut u8, MEM_LEN));
-
-        print_packet(slice::from_raw_parts_mut(ptr as *mut u8, MEM_LEN));
-    }
-    Ok(())
-}
-
-pub fn send(channel: usize, packet: &Packet) -> Result<(), Error> {
-    if unsafe { (CXP[channel].upconn_tx_enable_read)() } == 0 {
         Err(Error::LinkDown)?
     }
 
     match *packet {
-        Packet::TestPacket => send_test_packet(channel),
+        Packet::TestPacket => send_test_packet(),
-        _ => send_data_packet(channel, packet),
+        _ => send_data_packet(packet),
     }
 }
 
-fn send_data_packet(channel: usize, packet: &Packet) -> Result<(), Error> {
+fn send_data_packet(packet: &Packet) -> Result<(), Error> {
-    unsafe {
+    let mut buffer: [u8; MAX_PACKET] = [0; MAX_PACKET];
-        // TODO: put this in mem group
+    let mut writer = Cursor::new(&mut buffer[..]);
-        while (CXP[channel].upconn_command_tx_read)() == 1 {}
-        let ptr = CXP_TX_MEM[0].base as *mut u32;
-        let mut writer = Cursor::new(slice::from_raw_parts_mut(ptr as *mut u8, MEM_LEN));
 
     packet.write_to(&mut writer)?;
 
-        (CXP[channel].upconn_command_tx_word_len_write)(writer.position() as u8 / 4);
-        (CXP[channel].upconn_command_tx_write)(1);
-    }
-
-    Ok(())
-}
-
-fn send_test_packet(channel: usize) -> Result<(), Error> {
     unsafe {
-        while (CXP[channel].upconn_testseq_tx_read)() == 1 {}
+        let len = writer.position();
-        (CXP[channel].upconn_tx_testmode_en_write)(1);
+        csr::cxp::upconn_command_len_write(len as u8);
-        (CXP[channel].upconn_testseq_tx_write)(1);
+        for data in writer.get_ref()[..len].iter() {
-
+            while csr::cxp::upconn_command_writeable_read() == 0 {}
-        // wait till all test packet is out before switching back
+            csr::cxp::upconn_command_data_write(*data);
-        while (CXP[channel].upconn_testseq_tx_read)() == 1 {}
+        }
-        (CXP[channel].upconn_tx_testmode_en_write)(0);
     }
     Ok(())
 }
 
-pub fn write_u32(channel: usize, addr: u32, data: u32) -> Result<(), Error> {
+fn send_test_packet() -> Result<(), Error> {
+    unsafe {
+        while csr::cxp::upconn_tx_busy_read() == 1 {}
+        csr::cxp::upconn_tx_testmode_en_write(1);
+        csr::cxp::upconn_testseq_stb_write(1);
+        while csr::cxp::upconn_testseq_busy_read() == 1 {}
+        csr::cxp::upconn_tx_testmode_en_write(0);
+    }
+    Ok(())
+}
+
+pub fn write_u32(addr: u32, data: u32) -> Result<(), Error> {
     let mut data_slice: [u8; DATA_MAXSIZE] = [0; DATA_MAXSIZE];
     data_slice[..4].clone_from_slice(&data.to_be_bytes());
-    send(
+    send(&Packet::CtrlWrite {
-        channel,
-        &Packet::CtrlWrite {
         addr,
         length: 4,
         data: data_slice,
-        },
+    })?;
-    )?;
 
     Ok(())
 }
 
-pub fn read_u32(channel: usize, addr: u32) -> Result<(), Error> {
+pub fn read_u32(addr: u32) -> Result<(), Error> {
-    send(channel, &Packet::CtrlRead { addr, length: 4 })?;
+    send(&Packet::CtrlRead { addr, length: 4 })?;
 
     Ok(())
 }
 
-pub fn write_u64(channel: usize, addr: u32, data: u64) -> Result<(), Error> {
+pub fn write_u64(addr: u32, data: u64) -> Result<(), Error> {
     let mut data_slice: [u8; DATA_MAXSIZE] = [0; DATA_MAXSIZE];
     data_slice[..8].clone_from_slice(&data.to_be_bytes());
-    send(
+    send(&Packet::CtrlWrite {
-        channel,
-        &Packet::CtrlWrite {
         addr,
         length: 8,
         data: data_slice,
-        },
+    })?;
-    )?;
 
     Ok(())
 }
@@ -232,36 +211,71 @@ pub fn print_packetu32(pak: &[u32], k: &[u8]) {
     println!("============================================");
 }
 
-pub fn downconn_debug_send(channel: usize, packet: &Packet) -> Result<(), Error> {
+pub fn downconn_debug_send(packet: &Packet) -> Result<(), Error> {
-    unsafe {
+    let mut buffer: [u8; MAX_PACKET] = [0; MAX_PACKET];
-        // TODO: put this in mem group
+    let mut writer = Cursor::new(&mut buffer[..]);
-        while (CXP[channel].downconn_command_tx_read)() == 1 {}
-        let ptr = CXP_LOOPBACK_MEM[0].base as *mut u32;
-        let mut writer = Cursor::new(slice::from_raw_parts_mut(ptr as *mut u8, MEM_LEN));
 
     packet.write_to(&mut writer)?;
 
-        (CXP[channel].downconn_command_tx_word_len_write)(writer.position() as u8 / 4);
+    unsafe {
-        (CXP[channel].downconn_command_tx_write)(1);
+        csr::cxp::downconn_mux_sel_write(0);
+        let len = writer.position();
+        csr::cxp::downconn_debug_src_len_write(len as u8);
+        for data in writer.get_ref()[..len].iter() {
+            while csr::cxp::downconn_debug_src_writeable_read() == 0 {}
+            csr::cxp::upconn_command_data_write(*data);
+            csr::cxp::downconn_debug_src_data_write(*data);
+        }
     }
 
     Ok(())
 }
 
-pub fn downconn_debug_send_trig_ack(channel: usize) {
+pub fn downconn_debug_send_trig_ack() {
     unsafe {
-        (CXP[channel].downconn_ack_write)(1);
+        csr::cxp::downconn_mux_sel_write(1);
+        csr::cxp::downconn_ack_write(1);
     }
 }
 
-pub fn downconn_send_test_packet(channel: usize) {
+pub fn downconn_send_test_packet() {
     unsafe {
-        while (CXP[channel].downconn_testseq_tx_read)() == 1 {}
+        csr::cxp::downconn_mux_sel_write(2);
-        (CXP[channel].downconn_mux_sel_write)(1);
+        csr::cxp::downconn_testseq_stb_write(1);
-        (CXP[channel].downconn_testseq_tx_write)(1);
+        while csr::cxp::downconn_testseq_busy_read() == 1 {}
+    }
+}
 
-        // wait till all test packet is out before switching back
+pub fn ram_writer_send(packet: &Packet) -> Result<(), Error> {
-        while (CXP[channel].downconn_testseq_tx_read)() == 1 {}
+    unsafe {
-        (CXP[channel].downconn_mux_sel_write)(0);
+        // TODO: put this in mem group
+        while csr::cxp::transmitter_cxp_tx_read() == 1 {}
+        let ptr = CXP_MEM[0].base as *mut u32;
+        let mut writer = Cursor::new(slice::from_raw_parts_mut(ptr as *mut u8, 0x200 as usize));
+
+        packet.write_to(&mut writer)?;
+
+        csr::cxp::transmitter_cxp_tx_word_len_write(writer.position() as u8 / 4);
+        csr::cxp::transmitter_cxp_tx_write(1);
+        while csr::cxp::transmitter_cxp_tx_read() == 1 {}
+
+        // read the fifo
+        const LEN: usize = 10;
+        let mut pak_arr: [u32; LEN] = [0; LEN];
+        let mut k_arr: [u8; LEN] = [0; LEN];
+        let mut i: usize = 0;
+        while csr::cxp::transmitter_debug_out_dout_valid_read() == 1 {
+            pak_arr[i] = csr::cxp::transmitter_debug_out_dout_pak_read();
+            k_arr[i] = csr::cxp::transmitter_debug_out_kout_pak_read();
+            // println!("received {:#04X}", pak_arr[i]);
+            csr::cxp::transmitter_debug_out_inc_write(1);
+            i += 1;
+            if i == LEN {
+                break;
             }
         }
+        print_packetu32(&pak_arr, &k_arr);
+    }
+
+    Ok(())
+}

src/libboard_artiq/src/cxp_upconn.rs

@@ -1,42 +1,45 @@
+use core_io::{Error as IoError, Write};
+use crc::crc32;
 use embedded_hal::prelude::_embedded_hal_blocking_delay_DelayUs;
-use libboard_zynq::timer::GlobalTimer;
+use io::Cursor;
+use libboard_zynq::{println, timer::GlobalTimer};
 
 pub use crate::cxp_proto;
-use crate::pl::{csr, csr::CXP};
+use crate::pl::csr;
 
-pub fn tx_test(channel: usize, timer: &mut GlobalTimer) {
+pub fn tx_test(timer: &mut GlobalTimer) {
-    const LEN: usize = 4 * 30;
+    const LEN: usize = 4 * 50;
     let mut pak_arr: [u8; LEN] = [0; LEN];
 
     unsafe {
-        (CXP[channel].upconn_clk_reset_write)(1);
+        csr::cxp::upconn_clk_reset_write(1);
-        // CXP[channel].upconn_bitrate2x_enable_write(1);
+        // csr::cxp::upconn_bitrate2x_enable_write(1);
-        (CXP[channel].upconn_clk_reset_write)(0);
+        csr::cxp::upconn_clk_reset_write(0);
 
-        (CXP[channel].upconn_tx_enable_write)(1);
+        // read_u32(0x00).expect("Cannot Write CoaXpress Register");
+        csr::cxp::upconn_tx_enable_write(1);
         timer.delay_us(2); // send one word
-        cxp_proto::read_u32(channel, 0x00).expect("Cannot Write CoaXpress Register");
+        cxp_proto::send(&cxp_proto::Packet::EventAck { packet_tag: 0x04 }).expect("Cannot send CoaXpress packet");
-        // cxp_proto::write_u64(channel, 0x00, 0x01);
+        // cxp_proto::send(&cxp_proto::Packet::TestPacket).expect("Cannot send CoaXpress packet");
-        // cxp_proto::send(channel, &cxp_proto::Packet::EventAck { packet_tag: 0x04 }).expect("Cannot send CoaXpress packet");
-        // cxp_proto::send(channel, &cxp_proto::Packet::TestPacket).expect("Cannot send CoaXpress packet");
 
-        timer.delay_us(2);
+        // timer.delay_us(2);
         // DEBUG: Trigger packet
-        (CXP[channel].upconn_trig_delay_write)(0x86);
+        // let linktrig_mode: u8 = 0x01;
-        (CXP[channel].upconn_linktrigger_write)(0x00);
+        // csr::cxp::upconn_trig_delay_write(0x05);
-        (CXP[channel].upconn_trig_stb_write)(1); // send trig
+        // csr::cxp::upconn_linktrigger_write(linktrig_mode);
+        // csr::cxp::upconn_trig_stb_write(1); // send trig
 
         // DEBUG: Trigger ACK packet
-        // CXP[channel].upconn_ack_write(1);
+        // csr::cxp::upconn_ack_write(1);
-
         timer.delay_us(20);
-        (CXP[channel].upconn_tx_enable_write)(0);
+        csr::cxp::upconn_tx_enable_write(0);
 
         // Collect data
         let mut i: usize = 0;
-        while csr::cxp_phys::upconn_tx0_debug_buf_dout_valid_read() == 1 {
+        while csr::cxp::upconn_phy_debug_buf_dout_valid_read() == 1 {
-            pak_arr[i] = csr::cxp_phys::upconn_tx0_debug_buf_dout_pak_read();
+            pak_arr[i] = csr::cxp::upconn_phy_debug_buf_dout_pak_read();
-            csr::cxp_phys::upconn_tx0_debug_buf_inc_write(1);
+            // println!("received {:#04X}", pak_arr[i]);
+            csr::cxp::upconn_phy_debug_buf_inc_write(1);
             i += 1;
             if i == LEN {
                 break;

src/libboard_artiq/src/lib.rs

@@ -25,7 +25,7 @@ pub mod fiq;
 #[cfg(feature = "target_kasli_soc")]
 pub mod io_expander;
 pub mod logger;
-#[cfg(any(has_drtio, has_cxp_phys))]
+#[cfg(has_drtio)]
 #[rustfmt::skip]
 #[path = "../../../build/mem.rs"]
 pub mod mem;
@@ -42,9 +42,9 @@ pub mod si5324;
 pub mod si549;
 use core::{cmp, str};
 
-#[cfg(has_cxp_phys)]
+#[cfg(has_cxp)]
 pub mod cxp_downconn;
-#[cfg(has_cxp_phys)]
+#[cfg(has_cxp)]
 pub mod cxp_upconn;
 
 pub mod cxp_proto;

src/runtime/src/main.rs

@@ -151,18 +151,18 @@ pub fn main_core0() {
     task::spawn(ksupport::report_async_rtio_errors());
 
     cxp_downconn::setup(&mut timer);
-    // cxp_downconn::loopback_testing(0, &mut timer, cxp_downconn::CXP_SPEED::CXP_1);
+    cxp_downconn::loopback_testing(&mut timer, cxp_downconn::CXP_SPEED::CXP_1);
-    // cxp_downconn::loopback_testing(0, &mut timer, cxp_downconn::CXP_SPEED::CXP_2);
+    // cxp_downconn::loopback_testing(&mut timer, cxp_downconn::CXP_SPEED::CXP_2);
-    // cxp_downconn::loopback_testing(0, &mut timer, cxp_downconn::CXP_SPEED::CXP_3);
+    // cxp_downconn::loopback_testing(&mut timer, cxp_downconn::CXP_SPEED::CXP_3);
-    // cxp_downconn::loopback_testing(0, &mut timer, cxp_downconn::CXP_SPEED::CXP_5);
+    // cxp_downconn::loopback_testing(&mut timer, cxp_downconn::CXP_SPEED::CXP_5);
-    // cxp_downconn::loopback_testing(0, &mut timer, cxp_downconn::CXP_SPEED::CXP_6);
+    // cxp_downconn::loopback_testing(&mut timer, cxp_downconn::CXP_SPEED::CXP_6);
-    // cxp_downconn::loopback_testing(0, &mut timer, cxp_downconn::CXP_SPEED::CXP_10);
+    // cxp_downconn::loopback_testing(&mut timer, cxp_downconn::CXP_SPEED::CXP_10);
-    // cxp_downconn::loopback_testing(0, &mut timer, cxp_downconn::CXP_SPEED::CXP_12);
+    // cxp_downconn::loopback_testing(&mut timer, cxp_downconn::CXP_SPEED::CXP_12);
-    loop {
+    // loop {
-        use embedded_hal::prelude::_embedded_hal_blocking_delay_DelayUs;
+    //     use embedded_hal::prelude::_embedded_hal_blocking_delay_DelayUs;
-        cxp_upconn::tx_test(0, &mut timer);
+    //     cxp_upconn::tx_test(&mut timer);
-        timer.delay_us(5_000_000);
+    //     timer.delay_us(5_000_000);
-    }
+    // }
 
     comms::main(timer, cfg);
 }