forked from M-Labs/artiq-zynq
parent
12bf931614
commit
98095664ce
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@ -0,0 +1,193 @@
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use core_io::{Error as IoError, Write};
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use crc::crc32;
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use embedded_hal::prelude::_embedded_hal_blocking_delay_DelayUs;
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use io::Cursor;
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use libboard_zynq::{println, timer::GlobalTimer};
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use crate::pl::csr;
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const MAX_PACKET: usize = 128;
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const DATA_MAXSIZE: usize = /*max size*/MAX_PACKET - /*Tag*/4 - /*Op code & length*/4 - /*addr*/4 - /*CRC*/4 ;
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#[derive(Debug)]
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pub enum Error {
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BufferError,
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LinkDown,
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}
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impl From<IoError> for Error {
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fn from(_: IoError) -> Error {
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Error::BufferError
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}
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}
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pub enum Packet {
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CtrlRead {
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addr: u32,
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length: u8,
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},
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CtrlWrite {
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addr: u32,
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length: u8,
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data: [u8; DATA_MAXSIZE],
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}, // max register size is 8 bytes
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CtrlReadWithTag {
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tag: u8,
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addr: u32,
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length: u8,
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},
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CtrlWriteWithTag {
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tag: u8,
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addr: u32,
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length: u8,
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data: [u8; DATA_MAXSIZE],
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}, // max register size is 8 bytes
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EventAck {
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packet_tag: u8,
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},
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TestPacket,
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}
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impl Packet {
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pub fn write_to(&self, writer: &mut Cursor<&mut [u8]>) -> Result<(), Error> {
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// CoaXpress use big endian
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match *self {
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Packet::CtrlRead { addr, length } => {
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writer.write(&[0x02; 4])?;
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writer.write(&[0x00, 0x00, 0x00, length])?;
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writer.write(&addr.to_be_bytes())?;
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}
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Packet::CtrlWrite { addr, length, data } => {
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writer.write(&[0x02; 4])?;
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writer.write(&[0x01, 0x00, 0x00, length])?;
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writer.write(&addr.to_be_bytes())?;
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writer.write(&data[0..length as usize])?;
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}
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Packet::CtrlReadWithTag { tag, addr, length } => {
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writer.write(&[0x05; 4])?;
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writer.write(&[tag; 4])?;
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writer.write(&[0x00, 0x00, 0x00, length])?;
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writer.write(&addr.to_be_bytes())?;
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}
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Packet::CtrlWriteWithTag {
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tag,
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addr,
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length,
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data,
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} => {
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writer.write(&[0x05; 4])?;
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writer.write(&[tag; 4])?;
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writer.write(&[0x01, 0x00, 0x00, length])?;
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writer.write(&addr.to_be_bytes())?;
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writer.write(&data[0..length as usize])?;
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}
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Packet::EventAck { packet_tag } => {
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writer.write(&[0x08; 4])?;
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writer.write(&[packet_tag; 4])?;
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}
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_ => {}
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}
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// Section 9.2.2.2 (CXP-001-2021)
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// Only Control packet need CRC32 appended in the end of the packet
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// CoaXpress use the polynomial of IEEE-802.3 (Ethernet) CRC but the checksum calculation is different
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// Also, the calculation does not include the first 4 bytes of packet_type
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match *self {
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Packet::CtrlRead { .. }
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| Packet::CtrlWrite { .. }
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| Packet::CtrlReadWithTag { .. }
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| Packet::CtrlWriteWithTag { .. } => {
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let checksum = crc32::checksum_ieee(&writer.get_ref()[4..writer.position()]);
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writer.write(&(!checksum).to_le_bytes())?;
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}
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_ => {}
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}
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Ok(())
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}
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}
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pub fn send(packet: &Packet) -> Result<(), Error> {
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if unsafe { csr::cxp::upconn_tx_enable_read() } == 0 {
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Err(Error::LinkDown)?
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}
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match *packet {
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Packet::TestPacket => send_test_packet(),
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_ => send_data_packet(packet),
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}
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}
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fn send_data_packet(packet: &Packet) -> Result<(), Error> {
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let mut buffer: [u8; MAX_PACKET] = [0; MAX_PACKET];
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let mut writer = Cursor::new(&mut buffer[..]);
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packet.write_to(&mut writer)?;
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unsafe {
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let len = writer.position();
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csr::cxp::upconn_command_len_write(len as u8);
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for data in writer.get_ref()[..len].iter() {
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while csr::cxp::upconn_command_writeable_read() == 0 {}
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csr::cxp::upconn_command_data_write(*data);
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}
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}
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Ok(())
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}
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fn send_test_packet() -> Result<(), Error> {
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unsafe {
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while csr::cxp::upconn_tx_busy_read() == 1 {}
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csr::cxp::upconn_tx_testmode_en_write(1);
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// timer.delay_us(2);
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csr::cxp::upconn_testseq_stb_write(1);
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while csr::cxp::upconn_testseq_busy_read() == 1 {}
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csr::cxp::upconn_tx_testmode_en_write(0);
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}
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Ok(())
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}
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pub fn write_u32(addr: u32, data: u32) -> Result<(), Error> {
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let mut data_slice: [u8; DATA_MAXSIZE] = [0; DATA_MAXSIZE];
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data_slice[..4].clone_from_slice(&data.to_be_bytes());
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send(&Packet::CtrlWrite {
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addr,
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length: 4,
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data: data_slice,
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})?;
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Ok(())
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}
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pub fn read_u32(addr: u32) -> Result<(), Error> {
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send(&Packet::CtrlRead { addr, length: 4 })?;
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Ok(())
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}
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pub fn write_u64(addr: u32, data: u64) -> Result<(), Error> {
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let mut data_slice: [u8; DATA_MAXSIZE] = [0; DATA_MAXSIZE];
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data_slice[..8].clone_from_slice(&data.to_be_bytes());
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send(&Packet::CtrlWrite {
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addr,
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length: 8,
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data: data_slice,
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})?;
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Ok(())
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}
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// DEBUG: use only
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pub fn print_packet(pak: &[u8]) {
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println!("pak = [");
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for i in 0..(pak.len() / 4) {
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println!(
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"{:#03} {:#04X} {:#04X} {:#04X} {:#04X},",
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i + 1,
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pak[i * 4],
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pak[i * 4 + 1],
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pak[i * 4 + 2],
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pak[i * 4 + 3]
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)
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}
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println!("]");
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println!("============================================");
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}
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@ -47,6 +47,8 @@ pub mod cxp_downconn;
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#[cfg(has_cxp)]
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pub mod cxp_upconn;
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pub mod cxp_proto;
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pub fn identifier_read(buf: &mut [u8]) -> &str {
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unsafe {
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pl::csr::identifier::address_write(0);
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