pipeline gw: add rx bufout & refactor command pak

src/gateware/cxp_pipeline.py

@@ -6,6 +6,8 @@ from misoc.cores.liteeth_mini.mac.crc import LiteEthMACCRCEngine, LiteEthMACCRCC
 upconn_dw = 8
 upconn_layout = [("data", upconn_dw), ("k", upconn_dw//8)]
 
+downconn_dw = 32
+downconn_layout = [("data", downconn_dw), ("k", downconn_dw//8)]
 
 
 def K(x, y):
@@ -247,22 +249,22 @@ class Trigger_ACK(Module):
         self.source = k_code_inserter.source
 
 class TX_Command_Packet(Module, AutoCSR):
-    def __init__(self):
-        self.len = CSRStorage(6)
+        # Section 12.1.2 (CXP-001-2021)
+        # Max control packet size is 128 bytes
+    def __init__(self, fifo_depth=128):
+        self.len = CSRStorage(log2_int(fifo_depth))
         self.data = CSR(upconn_dw)
         self.writeable = CSRStatus()
 
         # # #
 
-        # Section 12.1.2 (CXP-001-2021)
-        # Max control packet size is 128 bytes
-        self.submodules.fifo = fifo = stream.SyncFIFO(upconn_layout, 128)
+        self.submodules.fifo = fifo = stream.SyncFIFO(upconn_layout, fifo_depth)
         self.submodules.pak_wrp = pak_wrp = Packet_Wrapper(upconn_layout)
         self.source = pak_wrp.source
 
         self.comb += fifo.source.connect(pak_wrp.sink)
 
-        len = Signal(6, reset=1)
+        cnt = Signal(log2_int(fifo_depth), reset=1)
         self.sync += [
             self.writeable.status.eq(fifo.sink.ack),
             If(fifo.sink.ack, fifo.sink.stb.eq(0)),
@@ -271,12 +273,12 @@ class TX_Command_Packet(Module, AutoCSR):
                 fifo.sink.data.eq(self.data.r),
 
                 fifo.sink.k.eq(0),
-                If(len == self.len.storage,
+                If(cnt == self.len.storage,
                     fifo.sink.eop.eq(1),
-                    len.eq(len.reset),
+                    cnt.eq(cnt.reset),
                 ).Else(
                     fifo.sink.eop.eq(0),
-                    len.eq(len + 1),
+                    cnt.eq(cnt + 1),
                 ),
             )
         ]
@@ -346,3 +348,21 @@ class TX_Test_Packet(Module, AutoCSR):
             ).Elif(self.source.eop & self.source.ack,
                 self.busy.status.eq(0)
             )
+
+class RX_Debug_Buffer(Module,AutoCSR):
+    def __init__(self):
+        self.submodules.buf_out = buf_out = stream.SyncFIFO(downconn_layout, 128)
+        self.sink = buf_out.sink
+
+        self.inc = CSR()
+        self.dout_pak = CSRStatus(downconn_dw)
+        self.kout_pak = CSRStatus(downconn_dw//8)
+        self.dout_valid = CSRStatus()
+
+        self.sync += [
+            # output
+            buf_out.source.ack.eq(self.inc.re),
+            self.dout_pak.status.eq(buf_out.source.data),
+            self.kout_pak.status.eq(buf_out.source.k),
+            self.dout_valid.status.eq(buf_out.source.stb),
+        ]