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cxp GW: rename phy

This commit is contained in:
morgan 2024-09-11 17:41:40 +08:00
parent 08ee4f1cb9
commit 8b2181b1a8
1 changed files with 8 additions and 8 deletions
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16
src/gateware/cxp.py
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@ -29,20 +29,20 @@ class UpConn_Interface(Module, AutoCSR):
layout = [("data", 8), ("k", 1)]
self.submodules.upconn_phy = upconn_phy = CXP_UpConn_PHY(upconn_pads, sys_clk_freq, debug_sma, pmod_pads, layout)
self.submodules.phy = phy = CXP_UpConn_PHY(upconn_pads, sys_clk_freq, debug_sma, pmod_pads, layout)
self.sync += [
upconn_phy.bitrate2x_enable.eq(self.bitrate2x_enable.storage),
upconn_phy.tx_enable.eq(self.tx_enable.storage),
upconn_phy.clk_reset.eq(self.clk_reset.re),
self.tx_busy.status.eq(upconn_phy.tx_busy),
phy.bitrate2x_enable.eq(self.bitrate2x_enable.storage),
phy.tx_enable.eq(self.tx_enable.storage),
phy.clk_reset.eq(self.clk_reset.re),
self.tx_busy.status.eq(phy.tx_busy),
]
# Packet FIFOs with transmission priority
# 0: Trigger packet
self.submodules.trig = trig = TX_Trigger(layout)
self.comb += trig.source.connect(upconn_phy.sinks[0])
self.comb += trig.source.connect(phy.sinks[0])
# DEBUG: INPUT
self.trig_stb = CSR()
@ -58,7 +58,7 @@ class UpConn_Interface(Module, AutoCSR):
# 1: IO acknowledgment for trigger packet
self.submodules.trig_ack = trig_ack = Trigger_ACK(layout)
self.comb += trig_ack.source.connect(upconn_phy.sinks[1])
self.comb += trig_ack.source.connect(phy.sinks[1])
# DEBUG: INPUT
self.ack = CSR()
@ -78,5 +78,5 @@ class UpConn_Interface(Module, AutoCSR):
testseq.source.connect(mux.sink1),
mux.sel.eq(self.tx_testmode_en.storage),
mux.source.connect(upconn_phy.sinks[2])
mux.source.connect(phy.sinks[2])
]