forked from M-Labs/artiq-zynq
pipeline GW: add test packet
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@ -278,3 +278,62 @@ class TX_Command_Packet(Module, AutoCSR):
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),
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)
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]
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class TX_Test_Packet(Module, AutoCSR):
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def __init__(self, layout):
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self.stb = CSR()
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# # #
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testdata_src = stream.Endpoint(layout)
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# Section 9.9.2 (CXP-001-2021)
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# 0x00, 0x01 ... 0xFF need to be send 16 times
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# cnt[8:12] is used to count up 16 times while cnt[:8] is the data
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cnt = Signal(max=0x1000)
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clr_cnt = Signal()
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inc_cnt = Signal()
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self.sync += [
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If(clr_cnt,
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cnt.eq(cnt.reset),
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).Elif(inc_cnt,
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cnt.eq(cnt + 1),
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),
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]
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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fsm.act("IDLE",
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clr_cnt.eq(1),
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If(self.stb.re,
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NextState("WRITE")
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)
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)
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fsm.act("WRITE",
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testdata_src.stb.eq(1),
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testdata_src.data.eq(cnt[:8]),
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testdata_src.k.eq(0),
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If(cnt == 0xFFF,
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testdata_src.eop.eq(1),
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If(testdata_src.ack, NextState("IDLE"))
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).Else(
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inc_cnt.eq(testdata_src.ack)
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)
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)
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self.submodules.pak_type_inserter = pak_type_inserter = Code_Inserter(layout)
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self.submodules.pak_wrp = pak_wrp = Packet_Wrapper(layout)
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self.comb += [
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pak_type_inserter.data.eq(0x04),
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pak_type_inserter.k.eq(0x04),
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testdata_src.connect(pak_type_inserter.sink),
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pak_type_inserter.source.connect(pak_wrp.sink),
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]
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self.source = pak_wrp.source
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