forked from M-Labs/artiq-zynq
cxp GW: add test packet & fix endian for downconn
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ef0ab1f526
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9178ca4576
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@ -26,16 +26,18 @@ class DownConn_Interface(Module, AutoCSR):
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# DEBUG: TX pipeline
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self.submodules.debug_src = debug_src = TX_Command_Packet()
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self.submodules.trig_ack = trig_ack = Trigger_ACK()
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self.submodules.mux = mux = stream.Multiplexer(upconn_layout, 2)
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self.submodules.conv = conv = stream.StrideConverter(upconn_layout, downconn_layout, reverse=True)
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self.submodules.testseq = testseq = TX_Test_Packet()
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self.submodules.mux = mux = stream.Multiplexer(upconn_layout, 3)
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self.submodules.conv = conv = stream.StrideConverter(upconn_layout, downconn_layout)
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self.ack = CSR()
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self.mux_sel = CSRStorage()
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self.mux_sel = CSRStorage(4)
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self.sync += trig_ack.ack.eq(self.ack.re),
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self.comb += [
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debug_src.source.connect(mux.sink0),
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trig_ack.source.connect(mux.sink1),
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testseq.source.connect(mux.sink2),
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mux.sel.eq(self.mux_sel.storage)
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]
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@ -54,9 +56,11 @@ class DownConn_Interface(Module, AutoCSR):
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self.packet_type = CSRStatus(8)
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self.decoder_error = CSRStatus()
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self.test_error = CSRStatus()
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self.comb += [
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self.packet_type.status.eq(recv_path.packet_type),
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self.decoder_error.status.eq(recv_path.decoder_err),
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self.test_error.status.eq(recv_path.test_err),
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]
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# DEBUG: CSR
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@ -67,6 +71,24 @@ class DownConn_Interface(Module, AutoCSR):
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recv_path.trig_clr.eq(self.trig_clr.re),
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]
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pak_start = Signal()
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self.sync += [
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pak_start.eq(recv_path.packet_decoder.sink.data == 0xFBFBFBFB),
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]
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self.specials += [
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# # pmod 0-7 pin
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Instance("OBUF", i_I=recv_path.packet_decoder.test_err, o_O=pmod_pads[0]),
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Instance("OBUF", i_I=pak_start, o_O=pmod_pads[1]),
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# Instance("OBUF", i_I=fifo_in.source.ack, o_O=pmod_pads[2]),
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# Instance("OBUF", i_I=gtx.comma_checker.aligner_en, o_O=pmod_pads[3]),
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# Instance("OBUF", i_I=gtx.comma_checker.check_reset, o_O=pmod_pads[4]),
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# Instance("OBUF", i_I=gtx.comma_checker.has_comma, o_O=pmod_pads[5]),
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# Instance("OBUF", i_I=gtx.comma_checker.has_error, o_O=pmod_pads[6]),
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# Instance("OBUF", i_I=gtx.comma_checker.ready_sys, o_O=pmod_pads[7]),
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]
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class UpConn_Interface(Module, AutoCSR):
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def __init__(self, upconn_pads, sys_clk_freq, debug_sma, pmod_pads):
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