forked from M-Labs/artiq-zynq
cxp pipeline: packet handling pipeline
tx pipeline: add CRC32 inserter tx pipeline: add start & end of packet code inserter tx pipeline: add packet wrapper for start & stop packet indication tx pipeline: add code source for trigger & trigger ack packet tx pipeline: add packet for trigger & trigger ack tx pipeline: add tx_command_packet for firmware tx command packet: add fifo to store control packet
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from migen import *
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from misoc.interconnect.csr import *
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from misoc.interconnect import stream
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from misoc.cores.liteeth_mini.mac.crc import LiteEthMACCRCEngine, LiteEthMACCRCChecker
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def K(x, y):
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return ((y << 5) | x)
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class Code_Source(Module):
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def __init__(self, layout, counts=4):
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self.source = stream.Endpoint(layout)
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self.stb = Signal()
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self.data = Signal.like(self.source.data)
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self.k = Signal.like(self.source.k)
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# # #
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cnt = Signal(max=counts)
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clr_cnt = Signal()
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inc_cnt = Signal()
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self.sync += [
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If(clr_cnt,
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cnt.eq(cnt.reset),
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).Elif(inc_cnt,
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cnt.eq(cnt + 1),
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)
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]
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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fsm.act("IDLE",
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clr_cnt.eq(1),
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If(self.stb,
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NextState("WRITE")
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)
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)
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fsm.act("WRITE",
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self.source.stb.eq(1),
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self.source.data.eq(self.data),
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self.source.k.eq(self.k),
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If(cnt == counts - 1,
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self.source.eop.eq(1),
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If(self.source.ack, NextState("IDLE"))
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).Else(
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inc_cnt.eq(self.source.ack)
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)
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)
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class Code_Inserter(Module):
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def __init__(self, layout, insert_infront=True, counts=4):
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self.sink = sink = stream.Endpoint(layout)
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self.source = source = stream.Endpoint(layout)
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self.data = Signal.like(sink.data)
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self.k = Signal.like(sink.k)
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# # #
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assert counts > 0
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cnt = Signal() if counts == 1 else Signal(max=counts)
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clr_cnt = Signal()
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inc_cnt = Signal()
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self.sync += [
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If(clr_cnt,
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cnt.eq(cnt.reset),
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).Elif(inc_cnt,
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cnt.eq(cnt + 1),
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)
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]
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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if insert_infront:
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fsm.act("IDLE",
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sink.ack.eq(1),
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clr_cnt.eq(1),
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If(sink.stb,
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sink.ack.eq(0),
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NextState("INSERT"),
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)
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)
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fsm.act("INSERT",
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sink.ack.eq(0),
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source.stb.eq(1),
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source.data.eq(self.data),
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source.k.eq(self.k),
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If(cnt == counts - 1,
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If(source.ack, NextState("COPY"))
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).Else(
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inc_cnt.eq(source.ack)
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)
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)
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fsm.act("COPY",
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sink.connect(source),
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If(sink.stb & sink.eop & source.ack,
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NextState("IDLE"),
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)
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)
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else:
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fsm.act("IDLE",
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sink.ack.eq(1),
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clr_cnt.eq(1),
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If(sink.stb,
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sink.ack.eq(0),
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NextState("COPY"),
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)
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)
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fsm.act("COPY",
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sink.connect(source),
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source.eop.eq(0),
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If(sink.stb & sink.eop & source.ack,
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NextState("INSERT"),
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)
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)
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fsm.act("INSERT",
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sink.ack.eq(0),
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source.stb.eq(1),
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source.data.eq(self.data),
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source.k.eq(self.k),
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If(cnt == counts - 1,
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source.eop.eq(1),
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If(source.ack, NextState("IDLE"))
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).Else(
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inc_cnt.eq(source.ack)
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),
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)
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class Packet_Wrapper(Module):
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def __init__(self, layout):
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self.submodules.pak_start = pak_start = Code_Inserter(layout)
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self.submodules.pak_end = pak_end = Code_Inserter(layout, insert_infront=False)
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self.sink = pak_start.sink
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self.source = pak_end.source
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self.comb += [
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pak_start.data.eq(K(27, 7)),
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pak_start.k.eq(1),
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pak_end.data.eq(K(29, 7)),
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pak_end.k.eq(1),
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pak_start.source.connect(pak_end.sink),
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]
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@ResetInserter()
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@CEInserter()
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class CXPCRC32(Module):
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# Section 9.2.2.2 (CXP-001-2021)
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width = 32
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polynom = 0x04C11DB7
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seed = 2**width-1
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check = 0x00000000
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def __init__(self, data_width):
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self.data = Signal(data_width)
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self.value = Signal(self.width)
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self.error = Signal()
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# # #
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self.submodules.engine = LiteEthMACCRCEngine(data_width, self.width, self.polynom)
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reg = Signal(self.width, reset=self.seed)
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self.sync += reg.eq(self.engine.next)
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self.comb += [
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self.engine.data.eq(self.data),
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self.engine.last.eq(reg),
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self.value.eq(reg[::-1]),
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self.error.eq(self.engine.next != self.check)
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]
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class CXPCRC32Checker(LiteEthMACCRCChecker):
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def __init__(self, layout):
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LiteEthMACCRCChecker.__init__(self, CXPCRC32, layout)
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class TX_Trigger(Module, AutoCSR):
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def __init__(self, layout):
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self.trig_stb = Signal()
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self.delay = Signal(8)
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self.linktrig_mode = Signal(max=4)
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# # #
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self.submodules.code_src = code_src = Code_Source(layout, counts=3)
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self.comb += [
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code_src.stb.eq(self.trig_stb),
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code_src.data.eq(self.delay),
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code_src.k.eq(0)
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]
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self.submodules.inserter_once = inserter_once = Code_Inserter(layout, counts=1)
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self.submodules.inserter_twice = inserter_twice = Code_Inserter(layout, counts=2)
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self.comb += [
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inserter_once.k.eq(1),
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inserter_twice.k.eq(1),
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If((self.linktrig_mode == 0) | (self.linktrig_mode == 2),
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inserter_once.data.eq(K(28, 2)),
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inserter_twice.data.eq(K(28, 4)),
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).Else(
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inserter_once.data.eq(K(28, 4)),
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inserter_twice.data.eq(K(28, 2)),
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)
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]
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tx_pipeline = [ code_src, inserter_twice, inserter_once]
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for s, d in zip(tx_pipeline, tx_pipeline[1:]):
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self.comb += s.source.connect(d.sink)
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self.source = tx_pipeline[-1].source
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class Trigger_ACK(Module):
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def __init__(self, layout):
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self.ack = Signal()
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# # #
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# Section 9.3.2 (CXP-001-2021)
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# Send 4x K28.6 and 4x 0x01 as trigger packet ack
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self.submodules.code_src = code_src = Code_Source(layout)
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self.submodules.k_code_inserter = k_code_inserter = Code_Inserter(layout)
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self.comb += [
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code_src.stb.eq(self.ack),
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code_src.data.eq(0x01),
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code_src.k.eq(0),
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k_code_inserter.data.eq(K(28, 6)),
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k_code_inserter.k.eq(1),
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code_src.source.connect(k_code_inserter.sink)
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]
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self.source = k_code_inserter.source
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class TX_Command_Packet(Module, AutoCSR):
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def __init__(self, layout):
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self.len = CSRStorage(6)
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self.data = CSR(8)
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self.writeable = CSRStatus()
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# # #
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# TODO: use RAM instead of FIFO ?
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# Section 12.1.2 (CXP-001-2021)
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# Max control packet size is 128 bytes
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# NOTE: The firmware will lock up if there is not enough space for the packet
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self.submodules.fifo = fifo = stream.SyncFIFO(layout, 128)
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self.submodules.pak_wrp = pak_wrp = Packet_Wrapper(layout)
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self.source = pak_wrp.source
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self.comb += fifo.source.connect(pak_wrp.sink)
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len = Signal(6, reset=1)
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self.sync += [
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self.writeable.status.eq(fifo.sink.ack),
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If(fifo.sink.ack, fifo.sink.stb.eq(0)),
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If(self.data.re,
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fifo.sink.stb.eq(1),
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fifo.sink.data.eq(self.data.r),
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fifo.sink.k.eq(0),
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If(len == self.len.storage,
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fifo.sink.eop.eq(1),
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len.eq(len.reset),
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).Else(
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fifo.sink.eop.eq(0),
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len.eq(len + 1),
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),
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)
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]
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