pipeline GW: use a common layout

src/gateware/cxp_pipeline.py

@@ -3,6 +3,11 @@ from misoc.interconnect.csr import *
 from misoc.interconnect import stream
 from misoc.cores.liteeth_mini.mac.crc import LiteEthMACCRCEngine, LiteEthMACCRCChecker
 
+upconn_dw = 8
+upconn_layout = [("data", upconn_dw), ("k", upconn_dw//8)]
+
+
+
 def K(x, y):
     return ((y << 5) | x)
 
@@ -184,22 +189,22 @@ class CXPCRC32Checker(LiteEthMACCRCChecker):
         LiteEthMACCRCChecker.__init__(self, CXPCRC32, layout)
 
 class TX_Trigger(Module, AutoCSR):
-    def __init__(self, layout):
+    def __init__(self):
         self.trig_stb = Signal()
-        self.delay = Signal(8) 
+        self.delay = Signal(upconn_dw) 
         self.linktrig_mode = Signal(max=4)
 
         # # #
 
-        self.submodules.code_src = code_src = Code_Source(layout, counts=3)
+        self.submodules.code_src = code_src = Code_Source(upconn_layout, counts=3)
         self.comb += [
             code_src.stb.eq(self.trig_stb),
             code_src.data.eq(self.delay),
             code_src.k.eq(0)
         ]
 
-        self.submodules.inserter_once = inserter_once = Code_Inserter(layout, counts=1)
-        self.submodules.inserter_twice = inserter_twice = Code_Inserter(layout, counts=2)
+        self.submodules.inserter_once = inserter_once = Code_Inserter(upconn_layout, counts=1)
+        self.submodules.inserter_twice = inserter_twice = Code_Inserter(upconn_layout, counts=2)
         self.comb += [
             inserter_once.k.eq(1),
             inserter_twice.k.eq(1),
@@ -220,15 +225,15 @@ class TX_Trigger(Module, AutoCSR):
         self.source = tx_pipeline[-1].source
 
 class Trigger_ACK(Module):
-    def __init__(self, layout):
+    def __init__(self):
         self.ack = Signal()
 
         # # #
 
         # Section 9.3.2 (CXP-001-2021)
         # Send 4x K28.6 and 4x 0x01 as trigger packet ack
-        self.submodules.code_src = code_src = Code_Source(layout)
-        self.submodules.k_code_inserter = k_code_inserter = Code_Inserter(layout)
+        self.submodules.code_src = code_src = Code_Source(upconn_layout)
+        self.submodules.k_code_inserter = k_code_inserter = Code_Inserter(upconn_layout)
         self.comb += [
             code_src.stb.eq(self.ack),
             code_src.data.eq(0x01),
@@ -242,17 +247,17 @@ class Trigger_ACK(Module):
         self.source = k_code_inserter.source
 
 class TX_Command_Packet(Module, AutoCSR):
-    def __init__(self, layout):
+    def __init__(self):
         self.len = CSRStorage(6)
-        self.data = CSR(8)
+        self.data = CSR(upconn_dw)
         self.writeable = CSRStatus()
 
         # # #
 
         # Section 12.1.2 (CXP-001-2021)
         # Max control packet size is 128 bytes
-        self.submodules.fifo = fifo = stream.SyncFIFO(layout, 128)
-        self.submodules.pak_wrp = pak_wrp = Packet_Wrapper(layout)
+        self.submodules.fifo = fifo = stream.SyncFIFO(upconn_layout, 128)
+        self.submodules.pak_wrp = pak_wrp = Packet_Wrapper(upconn_layout)
         self.source = pak_wrp.source
 
         self.comb += fifo.source.connect(pak_wrp.sink)
@@ -277,14 +282,14 @@ class TX_Command_Packet(Module, AutoCSR):
         ]
 
 class TX_Test_Packet(Module, AutoCSR):
-    def __init__(self, layout):
+    def __init__(self):
 
         self.stb = CSR()
         self.busy = CSRStatus()
 
         # # #
 
-        testdata_src = stream.Endpoint(layout)
+        testdata_src = stream.Endpoint(upconn_layout)
 
         
         # Section 9.9.2 (CXP-001-2021)
@@ -323,8 +328,8 @@ class TX_Test_Packet(Module, AutoCSR):
             )
         )
 
-        self.submodules.pak_type_inserter = pak_type_inserter = Code_Inserter(layout)
-        self.submodules.pak_wrp = pak_wrp = Packet_Wrapper(layout)
+        self.submodules.pak_type_inserter = pak_type_inserter = Code_Inserter(upconn_layout)
+        self.submodules.pak_wrp = pak_wrp = Packet_Wrapper(upconn_layout)
         self.comb += [
             pak_type_inserter.data.eq(0x04),
             pak_type_inserter.k.eq(0x04),