forked from M-Labs/artiq-zynq
upconn fw: add tx test packet csr control
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@ -19,7 +19,7 @@ impl From<IoError> for Error {
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}
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pub fn tx_test(timer: &mut GlobalTimer) {
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const LEN: usize = 4 * 20;
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const LEN: usize = 4 * 1000;
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let mut pak_arr: [u8; LEN] = [0; LEN];
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unsafe {
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@ -27,21 +27,23 @@ pub fn tx_test(timer: &mut GlobalTimer) {
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// csr::cxp::upconn_bitrate2x_enable_write(1);
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csr::cxp::upconn_clk_reset_write(0);
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send(&Packet::ControlU32Reg(Command::Read { addr: 0x00 })).expect("Cannot send CoaXpress packet");
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// send(&Packet::ControlU32Reg(Command::Read { addr: 0x00 })).expect("Cannot send CoaXpress packet");
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csr::cxp::upconn_tx_testmode_en_write(1);
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csr::cxp::upconn_tx_enable_write(1);
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timer.delay_us(2); // send one word
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csr::cxp::upconn_testseq_stb_write(1);
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timer.delay_us(2);
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// timer.delay_us(2);
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// DEBUG: Trigger packet
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let linktrig_mode: u8 = 0x01;
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csr::cxp::upconn_trig_delay_write(0x05);
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csr::cxp::upconn_linktrigger_write(linktrig_mode);
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csr::cxp::upconn_trig_stb_write(1); // send trig
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// let linktrig_mode: u8 = 0x01;
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// csr::cxp::upconn_trig_delay_write(0x05);
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// csr::cxp::upconn_linktrigger_write(linktrig_mode);
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// csr::cxp::upconn_trig_stb_write(1); // send trig
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// DEBUG: Trigger ACK packet
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// csr::cxp::upconn_ack_write(1);
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timer.delay_us(20);
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timer.delay_us(2000);
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csr::cxp::upconn_tx_enable_write(0);
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// Collect data
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