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artiq-zynq
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dowconn GW: rename csr

This commit is contained in:
morgan 2024-09-11 17:47:07 +08:00
parent b725594a1d
commit 12bf931614
1 changed files with 60 additions and 58 deletions
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118
src/libboard_artiq/src/cxp_downconn.rs
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@ -26,25 +26,25 @@ pub fn loopback_testing(timer: &mut GlobalTimer, speed: CXP_SPEED) {
timer.delay_us(50_000);
info!(
"tx_phaligndone = {} | rx_phaligndone = {}",
csr::cxp::downconn_txinit_phaligndone_read(),
csr::cxp::downconn_rxinit_phaligndone_read(),
csr::cxp::downconn_phy_txinit_phaligndone_read(),
csr::cxp::downconn_phy_rxinit_phaligndone_read(),
);
// enable txdata tranmission thought MGTXTXP, required by PMA loopback
csr::cxp::downconn_txenable_write(1);
csr::cxp::downconn_phy_txenable_write(1);
info!("waiting for rx to align...");
while csr::cxp::downconn_rx_ready_read() != 1 {}
while csr::cxp::downconn_phy_rx_ready_read() != 1 {}
info!("rx ready!");
loop {
// for _ in 0..20 {
// NOTE: raw bits
// let data0 = csr::cxp::downconn_rxdata_0_read();
// let data1 = csr::cxp::downconn_rxdata_1_read();
// let data2 = csr::cxp::downconn_rxdata_2_read();
// let data3 = csr::cxp::downconn_rxdata_3_read();
// let rxready = csr::cxp::downconn_rx_ready_read();
// let data0 = csr::cxp::downconn_phy_rxdata_0_read();
// let data1 = csr::cxp::downconn_phy_rxdata_1_read();
// let data2 = csr::cxp::downconn_phy_rxdata_2_read();
// let data3 = csr::cxp::downconn_phy_rxdata_3_read();
// let rxready = csr::cxp::downconn_phy_rx_ready_read();
// timer.delay_us(100);
// if data0 == 0b0101111100 || data0 == 0b1010000011 {
// println!(
@ -72,24 +72,24 @@ pub fn loopback_testing(timer: &mut GlobalTimer, speed: CXP_SPEED) {
timer.delay_us(1_000_000);
// NOTE: raw bits
// let data0 = csr::cxp::downconn_rxdata_0_read();
// let data1 = csr::cxp::downconn_rxdata_1_read();
// let data2 = csr::cxp::downconn_rxdata_2_read();
// let data3 = csr::cxp::downconn_rxdata_3_read();
// let data0 = csr::cxp::downconn_phy_rxdata_0_read();
// let data1 = csr::cxp::downconn_phy_rxdata_1_read();
// let data2 = csr::cxp::downconn_phy_rxdata_2_read();
// let data3 = csr::cxp::downconn_phy_rxdata_3_read();
// println!(
// "0b{:010b} {:010b} {:010b} {:010b}",
// data0, data1, data2, data3
// );
// NOTE:decode data
// let data0_k = csr::cxp::downconn_decoded_k_0_read();
// let data1_k = csr::cxp::downconn_decoded_k_1_read();
// let data2_k = csr::cxp::downconn_decoded_k_2_read();
// let data3_k = csr::cxp::downconn_decoded_k_3_read();
let data0_decoded = csr::cxp::downconn_decoded_data_0_read();
let data1_decoded = csr::cxp::downconn_decoded_data_1_read();
let data2_decoded = csr::cxp::downconn_decoded_data_2_read();
let data3_decoded = csr::cxp::downconn_decoded_data_3_read();
// let data0_k = csr::cxp::downconn_phy_decoded_k_0_read();
// let data1_k = csr::cxp::downconn_phy_decoded_k_1_read();
// let data2_k = csr::cxp::downconn_phy_decoded_k_2_read();
// let data3_k = csr::cxp::downconn_phy_decoded_k_3_read();
let data0_decoded = csr::cxp::downconn_phy_decoded_data_0_read();
let data1_decoded = csr::cxp::downconn_phy_decoded_data_1_read();
let data2_decoded = csr::cxp::downconn_phy_decoded_data_2_read();
let data3_decoded = csr::cxp::downconn_phy_decoded_data_3_read();
println!(
"{:#04x} {:#04x} {:#04x} {:#04x}",
data0_decoded, data1_decoded, data2_decoded, data3_decoded,
@ -108,24 +108,24 @@ pub fn loopback_testing(timer: &mut GlobalTimer, speed: CXP_SPEED) {
pub fn setup(timer: &mut GlobalTimer) {
unsafe {
info!("turning on pmc loopback mode...");
csr::cxp::downconn_loopback_mode_write(0b010); // Near-End PMA Loopback
csr::cxp::downconn_phy_loopback_mode_write(0b010); // Near-End PMA Loopback
// QPLL setup
csr::cxp::downconn_qpll_reset_write(1);
csr::cxp::downconn_phy_qpll_reset_write(1);
info!("waiting for QPLL/CPLL to lock...");
while csr::cxp::downconn_qpll_locked_read() != 1 {}
while csr::cxp::downconn_phy_qpll_locked_read() != 1 {}
info!("QPLL locked");
// tx/rx setup
csr::cxp::downconn_tx_start_init_write(1);
csr::cxp::downconn_rx_start_init_write(1);
csr::cxp::downconn_phy_tx_start_init_write(1);
csr::cxp::downconn_phy_rx_start_init_write(1);
info!("waiting for tx & rx setup...");
timer.delay_us(50_000);
info!(
"tx_phaligndone = {} | rx_phaligndone = {}",
csr::cxp::downconn_txinit_phaligndone_read(),
csr::cxp::downconn_rxinit_phaligndone_read(),
csr::cxp::downconn_phy_txinit_phaligndone_read(),
csr::cxp::downconn_phy_rxinit_phaligndone_read(),
);
}
@ -153,15 +153,15 @@ pub mod cxp_gtx {
change_cdr_cfg(speed);
unsafe {
csr::cxp::downconn_qpll_reset_write(1);
csr::cxp::downconn_phy_qpll_reset_write(1);
info!("waiting for QPLL/CPLL to lock...");
while csr::cxp::downconn_qpll_locked_read() != 1 {}
while csr::cxp::downconn_phy_qpll_locked_read() != 1 {}
info!("QPLL locked");
}
unsafe {
csr::cxp::downconn_tx_restart_write(1);
csr::cxp::downconn_rx_restart_write(1);
csr::cxp::downconn_phy_tx_restart_write(1);
csr::cxp::downconn_phy_rx_restart_write(1);
}
}
@ -245,19 +245,19 @@ pub mod cxp_gtx {
fn gtx_read(address: u16) -> u16 {
// DEBUG:
unsafe {
csr::cxp::downconn_gtx_daddr_write(address);
csr::cxp::downconn_gtx_dread_write(1);
while csr::cxp::downconn_gtx_dready_read() != 1 {}
csr::cxp::downconn_gtx_dout_read()
csr::cxp::downconn_phy_gtx_daddr_write(address);
csr::cxp::downconn_phy_gtx_dread_write(1);
while csr::cxp::downconn_phy_gtx_dready_read() != 1 {}
csr::cxp::downconn_phy_gtx_dout_read()
}
}
fn gtx_write(address: u16, value: u16) {
unsafe {
csr::cxp::downconn_gtx_daddr_write(address);
csr::cxp::downconn_gtx_din_write(value);
csr::cxp::downconn_gtx_din_stb_write(1);
while csr::cxp::downconn_gtx_dready_read() != 1 {}
csr::cxp::downconn_phy_gtx_daddr_write(address);
csr::cxp::downconn_phy_gtx_din_write(value);
csr::cxp::downconn_phy_gtx_din_stb_write(1);
while csr::cxp::downconn_phy_gtx_dready_read() != 1 {}
}
}
@ -265,19 +265,19 @@ pub mod cxp_gtx {
fn qpll_read(address: u8) -> u16 {
// DEBUG:
unsafe {
csr::cxp::downconn_qpll_daddr_write(address);
csr::cxp::downconn_qpll_dread_write(1);
while csr::cxp::downconn_qpll_dready_read() != 1 {}
csr::cxp::downconn_qpll_dout_read()
csr::cxp::downconn_phy_qpll_daddr_write(address);
csr::cxp::downconn_phy_qpll_dread_write(1);
while csr::cxp::downconn_phy_qpll_dready_read() != 1 {}
csr::cxp::downconn_phy_qpll_dout_read()
}
}
fn qpll_write(address: u8, value: u16) {
unsafe {
csr::cxp::downconn_qpll_daddr_write(address);
csr::cxp::downconn_qpll_din_write(value);
csr::cxp::downconn_qpll_din_stb_write(1);
while csr::cxp::downconn_qpll_dready_read() != 1 {}
csr::cxp::downconn_phy_qpll_daddr_write(address);
csr::cxp::downconn_phy_qpll_din_write(value);
csr::cxp::downconn_phy_qpll_din_stb_write(1);
while csr::cxp::downconn_phy_qpll_dready_read() != 1 {}
}
}
}
@ -301,43 +301,43 @@ pub mod txusrclk {
fn one_clock_cycle() {
unsafe {
csr::cxp::downconn_pll_dclk_write(1);
csr::cxp::downconn_pll_dclk_write(0);
csr::cxp::downconn_phy_pll_dclk_write(1);
csr::cxp::downconn_phy_pll_dclk_write(0);
}
}
fn set_addr(address: u8) {
unsafe {
csr::cxp::downconn_pll_daddr_write(address);
csr::cxp::downconn_phy_pll_daddr_write(address);
}
}
fn set_data(value: u16) {
unsafe {
csr::cxp::downconn_pll_din_write(value);
csr::cxp::downconn_phy_pll_din_write(value);
}
}
fn set_enable(en: bool) {
unsafe {
let val = if en { 1 } else { 0 };
csr::cxp::downconn_pll_den_write(val);
csr::cxp::downconn_phy_pll_den_write(val);
}
}
fn set_write_enable(en: bool) {
unsafe {
let val = if en { 1 } else { 0 };
csr::cxp::downconn_pll_dwen_write(val);
csr::cxp::downconn_phy_pll_dwen_write(val);
}
}
fn get_data() -> u16 {
unsafe { csr::cxp::downconn_pll_dout_read() }
unsafe { csr::cxp::downconn_phy_pll_dout_read() }
}
fn drp_ready() -> bool {
unsafe { csr::cxp::downconn_pll_dready_read() == 1 }
unsafe { csr::cxp::downconn_phy_pll_dready_read() == 1 }
}
#[allow(dead_code)]
@ -374,7 +374,7 @@ pub mod txusrclk {
fn reset(rst: bool) {
unsafe {
let val = if rst { 1 } else { 0 };
csr::cxp::downconn_txpll_reset_write(val)
csr::cxp::downconn_phy_txpll_reset_write(val)
}
}
@ -411,7 +411,7 @@ pub mod txusrclk {
// wait for the pll to lock
timer.delay_us(100);
let locked = unsafe { csr::cxp::downconn_txpll_locked_read() == 1 };
let locked = unsafe { csr::cxp::downconn_phy_txpll_locked_read() == 1 };
info!("txusrclk locked = {}", locked);
}
}
@ -540,3 +540,5 @@ pub mod txusrclk {
}
}
}
// TODO: add recv like in drtioaux