morgan
|
6134ad5794
|
cxp upconn: refactor idle into its submodule
|
2024-06-28 17:24:13 +08:00 |
morgan
|
dbf7ac1cb9
|
cxp upconn : fix idle word lag behind tx_wordcount
|
2024-06-28 15:46:13 +08:00 |
morgan
|
8ba7793b24
|
cxp upconn: fix word count issue
|
2024-06-28 12:46:35 +08:00 |
morgan
|
481162430c
|
cxp upconn: add word & char boundary transmission
|
2024-06-28 12:02:15 +08:00 |
morgan
|
4eed5e99f4
|
cxp upconn: put encoder with tx_fifos
|
2024-06-27 16:50:15 +08:00 |
morgan
|
98f4d4cea4
|
cxp upconn: refactor fifo into submodule
|
2024-06-27 12:51:20 +08:00 |
morgan
|
14a9184fee
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cxp upcxp: add tx_enable & startup sequence
|
2024-06-25 15:29:18 +08:00 |
morgan
|
ae4bfc40e5
|
cxp upconn: add priority packet
|
2024-06-24 14:59:49 +08:00 |
morgan
|
cdc7294e99
|
cxp upconn: add sys_clk_freq parameter to set pll
|
2024-06-20 16:20:27 +08:00 |
morgan
|
e6550c68cf
|
cxp upconn: add sink to txphy & cleanup
|
2024-06-20 15:57:37 +08:00 |
morgan
|
00e5d32d45
|
cxp upconn: add priority lv1 fifo & refactor
|
2024-06-20 14:56:28 +08:00 |
morgan
|
779084d5dc
|
cxp upconn: setup fifo
|
2024-06-20 10:57:05 +08:00 |
morgan
|
f43c8b8bac
|
cxp upconn: rename bits to tx_bitcount
|
2024-06-18 16:42:17 +08:00 |
morgan
|
6636339701
|
cxp upconn: refactor serial fsm as sync logic
|
2024-06-18 16:40:40 +08:00 |
morgan
|
bd66659883
|
cxp upconn: write state fsm refactor
|
2024-06-18 15:58:53 +08:00 |
morgan
|
4de58e0d52
|
cxp upconn: use singlencoder & fix disparity bug
|
2024-06-18 14:40:58 +08:00 |
morgan
|
7c60fb5776
|
cxp upconn: init encoder
|
2024-06-18 12:26:10 +08:00 |
morgan
|
bbf9e37867
|
cxp upconn: rename high speed upconn to bitrate2x
|
2024-06-18 12:24:31 +08:00 |
morgan
|
d36afd6f7b
|
CXP upconn: add sys reset signal to pll
|
2024-06-17 16:51:55 +08:00 |
morgan
|
cb1ec7f62a
|
CXP upconn: remove unused code
|
2024-06-17 14:46:49 +08:00 |
morgan
|
48d3a9cd4a
|
CXP up connection gw: init
|
2024-06-17 13:19:37 +08:00 |
morgan
|
96a052513d
|
zc706: use new CXP file name
|
2024-06-14 17:18:26 +08:00 |
morgan
|
b2c6c20426
|
cxp: refactor to its separte module
|
2024-06-14 17:17:56 +08:00 |
morgan
|
5fcf5cb70f
|
cxp gtx: rename to cxp_downconn
|
2024-06-14 17:17:16 +08:00 |
morgan
|
47e1a83519
|
cxp fmc: rename file
|
2024-06-14 17:16:51 +08:00 |
morgan
|
d592825284
|
CXP gtx: rename to CXP DownConn
|
2024-06-14 17:07:58 +08:00 |
morgan
|
b52589bd5f
|
CXP CLK alignment: clock domain naming refactor
|
2024-06-13 16:56:36 +08:00 |
morgan
|
9c69167f7f
|
CXP gtx: Clock domain naming refactor and remove cxp_gtx
|
2024-06-13 16:56:16 +08:00 |
morgan
|
8ac71b37a9
|
CXP GTX: init
|
2024-06-12 14:50:38 +08:00 |
morgan
|
ce0e14879c
|
Gateware: ZC706 CXP GTX setup
|
2024-06-05 13:02:52 +08:00 |
morgan
|
df7feb3b17
|
Gateware: CXP_GTX init
|
2024-06-05 13:02:52 +08:00 |
morgan
|
f5c604bbb5
|
zc706: add USER LED to allow compilation
|
2024-06-05 13:02:29 +08:00 |
morgan
|
d61d7a5a95
|
zc706: add CXP FMC variant
|
2024-06-05 13:02:29 +08:00 |
morgan
|
681d7400c7
|
FMCIO: add cxp_4r adepter io
|
2024-06-05 13:02:29 +08:00 |
morgan
|
9f2f392728
|
flake: add CXP_FMC variant build options
|
2024-06-05 13:02:29 +08:00 |
morgan
|
586fd2f17e
|
Gateware: remove redundant si549.py & wrpll.py
|
2024-05-30 15:27:16 +08:00 |
morgan
|
377f8779a0
|
kasli soc: refactor to use wrpll from artiq
|
2024-05-30 15:25:33 +08:00 |
morgan
|
1fbaacfc43
|
flake: update artiq
|
2024-05-30 15:14:02 +08:00 |
Sebastien Bourdeauducq
|
127ea9ea4d
|
flake: update dependencies
|
2024-05-28 17:30:49 +08:00 |
Simon Renblad
|
174c301d7d
|
add llvmPackages_11
|
2024-05-24 15:29:29 +08:00 |
Sebastien Bourdeauducq
|
52defff000
|
flake: update dependencies
|
2024-05-24 15:29:19 +08:00 |
mwojcik
|
2b2ebb5354
|
aux: increase max payload size
|
2024-05-20 15:20:06 +08:00 |
Sebastien Bourdeauducq
|
4341d2d2a5
|
update to LLLVM 14
|
2024-05-09 10:05:33 +08:00 |
Sebastien Bourdeauducq
|
57b885ed99
|
flake: update dependencies
|
2024-05-09 10:03:57 +08:00 |
Sebastien Bourdeauducq
|
e922543855
|
flake: update dependencies
|
2024-05-08 18:56:15 +08:00 |
morgan
|
35ea0ed2ca
|
WRPLL: add filter for DRTIO 100MHz
|
2024-05-08 18:50:55 +08:00 |
morgan
|
cdf4ff24c0
|
WRPLL: replace PI controller with new filter
|
2024-05-08 18:50:55 +08:00 |
morgan
|
285b02c4b1
|
WRPLL: remove anti-windup
|
2024-05-08 18:50:55 +08:00 |
morgan
|
53cb592d19
|
kasli soc: add rtio_frequency cfg for runtime
|
2024-05-08 16:14:56 +08:00 |
Florian Agbuya
|
c261897658
|
rename `build` derivation to `board-package-set`
|
2024-04-29 13:05:49 +08:00 |