forked from M-Labs/artiq-zynq
CXP upconn: remove unused code
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@ -4,45 +4,7 @@ from migen.genlib.cdc import MultiReg
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from misoc.cores.code_8b10b import Encoder, Decoder
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from misoc.interconnect.csr import *
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class CXP_Serial(Module):
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def __init__(self, tx_width=10):
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self.o = Signal()
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self.write = Signal()
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self.data = Signal(tx_width)
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self.busy = Signal()
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# # #
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bits = Signal(max=tx_width)
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data = Signal(tx_width)
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fsm = ClockDomainsRenamer("cd_cxp_upconn")(FSM(reset_state="IDLE"))
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fsm.act("IDLE",
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NextValue(self.o, 0),
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If(self.write,
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NextValue(bits, tx_width),
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NextValue(data, self.data),
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NextState("WRITE")
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)
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)
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fsm.act("WRITE",
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If(bits == 0,
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NextValue(self.o, 0),
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NextState("IDLE")
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),
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NextValue(bits, bits - 1),
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NextValue(self.o, data[0]),
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NextValue(data, Cat(data[1:], 0)),
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)
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self.comb += self.busy.eq(~fsm.ongoing("IDLE"))
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from misoc.interconnect import stream
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class CXP_UpConn(Module, AutoCSR):
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def __init__(self, pads, tx_width=10):
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