morgan
/
artiq-zynq
forked from M-Labs/artiq-zynq
1
0
Fork 0
Code Pull Requests Activity

cxp upconn: refactor serial fsm as sync logic

This commit is contained in:
morgan 2024-06-18 16:40:40 +08:00
parent bd66659883
commit 6636339701
1 changed files with 12 additions and 30 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

42
src/gateware/cxp_upconn.py
View File

@ -58,37 +58,8 @@ class CXP_UpConn(Module, AutoCSR):
o = Signal()
bits = Signal(max=tx_width)
tx_reg = Signal(tx_width)
busy = Signal()
self.submodules.fsm = ClockDomainsRenamer("cxp_upconn")(FSM(reset_state="IDLE"))
self.submodules.encoder = SingleEncoder(True)
self.fsm.act("IDLE",
NextValue(o, 0),
If(self.stb.storage,
NextValue(bits, 0),
NextValue(tx_reg, self.encoder.output),
NextValue(self.tx_reg.status, self.encoder.output),
NextValue(self.encoder.disp_in, self.encoder.disp_out),
NextState("WRITE")
)
)
self.fsm.act("WRITE",
NextValue(o, tx_reg[0]),
NextValue(tx_reg, Cat(tx_reg[1:], 0)),
If(bits == tx_width - 1,
If(self.stb.storage,
NextValue(bits, 0),
NextValue(tx_reg, self.encoder.output),
NextValue(self.tx_reg.status, self.encoder.output),
NextValue(self.encoder.disp_in, self.encoder.disp_out),
).Else(
NextState("IDLE"),
),
).Else(
NextValue(bits, bits + 1)
)
)
self.comb += [
self.encoder.d.eq(self.data.storage),
@ -97,9 +68,20 @@ class CXP_UpConn(Module, AutoCSR):
self.sync.cxp_upconn +=[
self.encoded.status.eq(self.encoder.output),
If(self.stb.storage,
o.eq(tx_reg[0]),
tx_reg.eq(Cat(tx_reg[1:], 0))
),
If(bits != tx_width - 1,
bits.eq(bits + 1),
).Elif(self.stb.storage,
bits.eq(0),
tx_reg.eq(self.encoder.output),
self.tx_reg.status.eq(self.encoder.output),
self.encoder.disp_in.eq(self.encoder.disp_out),
)
]
self.comb += busy.eq(~self.fsm.ongoing("IDLE"))
# DEBUG: remove pads
self.specials += [
Instance("OBUF", i_I=o, o_O=pads.p_tx),