forked from M-Labs/artiq-zynq
cxp upconn: rename bits to tx_bitcount
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@ -56,7 +56,7 @@ class CXP_UpConn(Module, AutoCSR):
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o = Signal()
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bits = Signal(max=tx_width)
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tx_bitcount = Signal(max=tx_width)
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tx_reg = Signal(tx_width)
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self.submodules.encoder = SingleEncoder(True)
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@ -72,10 +72,10 @@ class CXP_UpConn(Module, AutoCSR):
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o.eq(tx_reg[0]),
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tx_reg.eq(Cat(tx_reg[1:], 0))
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),
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If(bits != tx_width - 1,
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bits.eq(bits + 1),
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If(tx_bitcount != tx_width - 1,
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tx_bitcount.eq(tx_bitcount + 1),
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).Elif(self.stb.storage,
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bits.eq(0),
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tx_bitcount.eq(0),
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tx_reg.eq(self.encoder.output),
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self.tx_reg.status.eq(self.encoder.output),
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self.encoder.disp_in.eq(self.encoder.disp_out),
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