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master 586fd2f17e · Gateware: remove redundant si549.py & wrpll.py · Updated 2024-05-30 15:27:16 +08:00

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coax_proto 8822fcbc1d · sim: prototyping frame decoding pipeine · Updated 2024-11-13 16:16:49 +08:00    morgan	0 41	Compare	ZIP  TAR.GZ
refactor_wrpll 586fd2f17e · Gateware: remove redundant si549.py & wrpll.py · Updated 2024-05-30 15:27:16 +08:00	0 0	M-Labs/artiq-zynq#300 Merged	ZIP  TAR.GZ
new_filter 76c285cc87 · WRPLL: add filter for DRTIO 100MHz · Updated 2024-05-08 16:22:35 +08:00	14 3	M-Labs/artiq-zynq#296 Merged	ZIP  TAR.GZ
rtio_fix 53cb592d19 · kasli soc: add rtio_frequency cfg for runtime · Updated 2024-05-08 16:14:56 +08:00	13 0	M-Labs/artiq-zynq#295 Merged	ZIP  TAR.GZ
filter 4700d4c9ed · WRPLL: remove anti-windup · Updated 2024-05-07 16:34:44 +08:00	14 2	Compare	ZIP  TAR.GZ
DDMTD 11072f3aff · Si549: recalibrate TAG_OFFSET for ISERDESE2 · Updated 2024-04-29 12:05:42 +08:00	26 2	M-Labs/artiq-zynq#292 Merged	ZIP  TAR.GZ
wrpll_mmcm_fix a597d0b8e2 · wrpll runtime: reduce mmcm output jitter · Updated 2024-04-26 15:42:21 +08:00	26 2	M-Labs/artiq-zynq#294 Merged	ZIP  TAR.GZ
deglitcher 7b8b0d1ef0 · DDMTD: replace 1st edge to median edge deglitcher · Updated 2024-04-26 13:07:02 +08:00	26 1	M-Labs/artiq-zynq#293 Merged	ZIP  TAR.GZ
WRPLL 14fa038118 · Firmware: Runtime WRPLL · Updated 2024-04-12 16:38:46 +08:00	26 0	M-Labs/artiq-zynq#282 Merged	ZIP  TAR.GZ
vector_fix 4455f740d2 · main: set exception vector table addr · Updated 2024-03-07 15:37:42 +08:00	34 0	M-Labs/artiq-zynq#288 Merged	ZIP  TAR.GZ
fiq_issue adaecf87a8 · FIQ_issue · Updated 2024-03-04 12:03:53 +08:00	36 13	Compare	ZIP  TAR.GZ
testing bfbea2d0b8 · testing only · Updated 2024-03-04 11:37:43 +08:00	36 13	Compare	ZIP  TAR.GZ
release-7 3da71dedd7 · kasli_soc: use sed_lanes value from HW description · Updated 2024-01-30 16:17:49 +08:00	188 40	Compare	ZIP  TAR.GZ
release-6 0c1036cb0c · qc2: add 4 edge counters to the end of rtio · Updated 2023-04-03 12:39:43 +08:00	335 11	Compare	ZIP  TAR.GZ