forked from M-Labs/artiq-zynq
cxp upconn: refactor fifo into submodule
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14a9184fee
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@ -3,18 +3,16 @@ from migen.genlib.resetsync import AsyncResetSynchronizer
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from migen.genlib.coding import PriorityEncoder
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from misoc.cores.code_8b10b import SingleEncoder
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from misoc.interconnect.csr import *
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from misoc.interconnect import stream
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from misoc.interconnect.csr import *
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# CXP2.1 section 9.2.5
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# CXP 2.1 section 9.2.5
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IDLE_WORDS = [
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#[k, data]
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#[data, k]
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[0b10111100, 1], #K28.5
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[0b10111100, 1], #K28.5
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# TODO: fix index error for this crap
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[0b00111100, 1], #K28.1
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[0b00111100, 1], #K28.1
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# Cat(0b10111100, 0), #D28.5
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[0b10111100, 0], #D28.5
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]
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@ -25,8 +23,6 @@ class CXP_UpConn(Module, AutoCSR):
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self.bitrate2x_enable = CSRStorage()
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self.tx_enable = CSRStorage()
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self.tx_fifos = []
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# # #
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pll_locked = Signal()
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@ -62,103 +58,76 @@ class CXP_UpConn(Module, AutoCSR):
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AsyncResetSynchronizer(self.cd_cxp_upconn, ~pll_locked | self.clk_reset.storage)
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]
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# self.submodules.phy = UpConnTXPHY(pads)
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# FIFOs with transmission priority
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# 0: Trigger packet
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# 1: IO acknowledgment for trigger packet
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# 2: All other packets
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sinks_full = Signal(nfifos)
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sources_stb = Signal(nfifos)
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sources_ack = Array(Signal() for _ in range(nfifos))
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sources_data = Array(Signal(9) for _ in range(nfifos))
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for i in range(nfifos):
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cdr = ClockDomainsRenamer({"write": "sys", "read": "cxp_upconn"})
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fifo = cdr(stream.AsyncFIFO([("data", 9)], fifo_depth))
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self.tx_fifos.append(fifo)
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setattr(self.submodules, "tx_fifo" + str(i), fifo)
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self.comb += [
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sinks_full[i].eq(fifo.sink.ack),
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fifo.source.ack.eq(sources_ack[i]),
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sources_stb[i].eq(fifo.source.stb),
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sources_data[i].eq(fifo.source.data),
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]
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# setup pulse ack
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self.sync.cxp_upconn += sources_ack[i].eq(0)
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self.submodules.pe = PriorityEncoder(nfifos)
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self.comb += self.pe.i.eq(sources_stb)
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idle_word_count = Signal(max=len(IDLE_WORDS))
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self.submodules.fsm = ClockDomainsRenamer("cxp_upconn")(FSM(reset_state="WAIT_TX_ENABLE"))
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self.submodules.encoder = ClockDomainsRenamer("cxp_upconn")(SingleEncoder(True))
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self.submodules.tx_fifos = TxFIFOs(nfifos, fifo_depth)
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fsm = ClockDomainsRenamer("cxp_upconn")(FSM(reset_state="WAIT_TX_ENABLE"))
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self.submodules += fsm
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o = Signal()
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tx_en = Signal()
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tx_bitcount = Signal(max=10)
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tx_reg = Signal(10)
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encoded = Signal()
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stb = Signal()
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idleidx = Signal(max=len(IDLE_WORDS))
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fsm.act("WAIT_TX_ENABLE",
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# startup sequence
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self.fsm.act("WAIT_TX_ENABLE",
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If(self.tx_enable.storage,
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NextState("ENCODE_IDLE_WORD")
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)
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)
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fsm.act("ENCODE_IDLE_WORD",
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self.fsm.act("ENCODE_IDLE_WORD",
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NextValue(self.encoder.d, IDLE_WORDS[0][0]),
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NextValue(self.encoder.k, IDLE_WORDS[0][1]),
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NextValue(self.encoder.disp_in, 0),
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NextValue(idle_word_count, 1),
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NextValue(idleidx, 1),
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NextState("START_TX")
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)
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fsm.act("START_TX",
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self.fsm.act("START_TX",
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tx_en.eq(1),
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If((~self.tx_enable.storage) & (tx_bitcount == 9),
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NextState("WAIT_TX_ENABLE")
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)
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)
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self.sync.cxp_upconn +=[
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# CXP 2.1 section 9.2.4
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self.sync.cxp_upconn += [
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If(tx_en,
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o.eq(tx_reg[0]),
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tx_reg.eq(Cat(tx_reg[1:], 0)),
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tx_bitcount.eq(tx_bitcount + 1),
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If(tx_bitcount == 8,
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If(~self.pe.n,
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self.encoder.d.eq(sources_data[self.pe.o][:8]),
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self.encoder.k.eq(sources_data[self.pe.o][8]),
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sources_ack[self.pe.o].eq(1),
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# TODO: only allow trigger packet to do character interrupt and other priority level to only interrupt word
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If(~self.tx_fifos.pe.n,
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self.encoder.d.eq(self.tx_fifos.source_data[self.tx_fifos.pe.o][:8]),
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self.encoder.k.eq(self.tx_fifos.source_data[self.tx_fifos.pe.o][8]),
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self.tx_fifos.source_ack[self.tx_fifos.pe.o].eq(1),
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).Else(
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self.encoder.d.eq(Array(IDLE_WORDS)[idle_word_count][0]),
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self.encoder.k.eq(Array(IDLE_WORDS)[idle_word_count][1]),
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If(idle_word_count != len(IDLE_WORDS),
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idle_word_count.eq(idle_word_count + 1)
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self.encoder.d.eq(Array(IDLE_WORDS)[idleidx][0]),
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self.encoder.k.eq(Array(IDLE_WORDS)[idleidx][1]),
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If(idleidx != len(IDLE_WORDS),
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idleidx.eq(idleidx + 1)
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).Else(
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idle_word_count.eq(0)
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idleidx.eq(0)
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)
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)
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).Elif(tx_bitcount == 9,
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tx_bitcount.eq(0),
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tx_reg.eq(self.encoder.output),
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self.encoder.disp_in.eq(self.encoder.disp_out),
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tx_bitcount.eq(0),
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tx_reg.eq(self.encoder.output),
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self.encoder.disp_in.eq(self.encoder.disp_out),
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)
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).Else(
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o.eq(0)
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)
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]
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# DEBUG: remove pads
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self.idle_word_index = CSRStatus()
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self.encoded_data = CSRStatus(10)
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self.sync.cxp_upconn +=[
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self.idle_word_index.status.eq(idle_word_count)
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If(tx_bitcount == 9,
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self.encoded_data.status.eq(self.encoder.output),
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)
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]
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ninth_bit = Signal()
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@ -169,8 +138,8 @@ class CXP_UpConn(Module, AutoCSR):
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self.comb += [
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eighth_bit.eq(tx_bitcount == 8),
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ninth_bit.eq(tx_bitcount == 9),
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idle_3.eq(idle_word_count == 3),
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idle_2.eq(idle_word_count == 2),
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idle_3.eq(idleidx == 3),
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idle_2.eq(idleidx == 2),
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]
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self.specials += [
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# debug sma
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@ -180,41 +149,53 @@ class CXP_UpConn(Module, AutoCSR):
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# pmod 0-7 pin
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Instance("OBUF", i_I=o, o_O=pmod[0]),
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Instance("OBUF", i_I=self.cd_cxp_upconn.clk, o_O=pmod[1]),
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Instance("OBUF", i_I=tx_en, o_O=pmod[2]),
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Instance("OBUF", i_I=idle_3, o_O=pmod[3]),
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Instance("OBUF", i_I=~self.tx_fifos.pe.n, o_O=pmod[2]),
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Instance("OBUF", i_I=ninth_bit, o_O=pmod[3]),
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Instance("OBUF", i_I=idle_2, o_O=pmod[4]),
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# Instance("OBUF", i_I=eighth_bit, o_O=pmod[3]),
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# Instance("OBUF", i_I=ninth_bit, o_O=pmod[4]),
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Instance("OBUF", i_I=encoded, o_O=pmod[5]),
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Instance("OBUF", i_I=~self.pe.n, o_O=pmod[6]),
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Instance("OBUF", i_I=self.tx_fifos.source_ack[0], o_O=pmod[5]),
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Instance("OBUF", i_I=idle_3, o_O=pmod[6]),
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Instance("OBUF", i_I=tx_en, o_O=pmod[7]),
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]
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self.symbol0 = CSR(9)
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self.symbol1 = CSR(9)
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self.sync += [
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self.tx_fifos[0].sink.stb.eq(self.symbol0.re),
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self.tx_fifos[0].sink.data.eq(self.symbol0.r),
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self.tx_fifos[1].sink.stb.eq(self.symbol1.re),
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self.tx_fifos[1].sink.data.eq(self.symbol1.r),
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# self.fifo_full[i].eq(~fifo.sink.ack),
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self.tx_fifos.sink_stb[0].eq(self.symbol0.re),
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self.tx_fifos.sink_data[0].eq(self.symbol0.r),
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self.tx_fifos.sink_stb[1].eq(self.symbol1.re),
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self.tx_fifos.sink_data[1].eq(self.symbol1.r),
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]
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class UpConnTXPHY(Module, AutoCSR):
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def __init__(self, pads):
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self.sink = stream.Endpoint([("data", 9)])
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class TxFIFOs(Module, AutoCSR):
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def __init__(self, nfifos, fifo_depth):
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self.sink_stb = Signal(nfifos)
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self.sink_ack = Signal(nfifos)
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self.sink_data = [Signal(9) for _ in range(nfifos)]
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# data & ack will be used dynamically during runtime, cannot use python array
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self.source_stb = Signal(nfifos)
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self.source_ack = Array(Signal() for _ in range(nfifos))
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self.source_data = Array(Signal(9) for _ in range(nfifos))
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# # #
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self.submodules.encoder = ClockDomainsRenamer("cxp_upconn")(SingleEncoder(True))
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for i in range(nfifos):
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cdr = ClockDomainsRenamer({"write": "sys", "read": "cxp_upconn"})
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fifo = cdr(stream.AsyncFIFO([("data", 9)], fifo_depth))
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setattr(self.submodules, "tx_fifo" + str(i), fifo)
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self.comb += [
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fifo.sink.stb.eq(self.sink_stb[i]),
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self.sink_ack[i].eq(fifo.sink.ack),
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fifo.sink.data.eq(self.sink_data[i]),
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self.comb += [
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self.encoder.d.eq(self.sink.data[:8]),
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self.encoder.k.eq(self.sink.data[8])
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]
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self.source_stb[i].eq(fifo.source.stb),
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fifo.source.ack.eq(self.source_ack[i]),
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self.source_data[i].eq(fifo.source.data),
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]
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# reset ack after asserted
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self.sync.cxp_upconn += If(self.source_ack[i], self.source_ack[i].eq(0))
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# For FIFOs transmission priority
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self.submodules.pe = PriorityEncoder(nfifos)
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self.comb += self.pe.i.eq(self.source_stb)
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o = Signal()
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tx_en = Signal()
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tx_bitcount = Signal(max=10)
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tx_reg = Signal(10)
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self.specials += Instance("OBUF", i_I=o, o_O=pads.p_tx)
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