forked from M-Labs/artiq-zynq
WRPLL: remove anti-windup
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53cb592d19
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285b02c4b1
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@ -337,8 +337,6 @@ pub mod wrpll {
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const KP: i32 = 6;
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const KI: i32 = 2;
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// 4 ppm capture range
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const ADPLL_LIM: i32 = (4.0 / 0.0001164) as i32;
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static mut BASE_ADPLL: i32 = 0;
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static mut H_LAST_ADPLL: i32 = 0;
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@ -520,7 +518,7 @@ pub mod wrpll {
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let period_err = tag_collector::get_period_error();
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unsafe {
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// Based on https://hackmd.io/IACbwcOTSt6Adj3_F9bKuw?view#Integral-wind-up-and-output-limiting
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let adpll = (H_LAST_ADPLL + (KP + KI) * period_err - KP * LAST_PERIOD_ERR).clamp(-ADPLL_LIM, ADPLL_LIM);
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let adpll = H_LAST_ADPLL + (KP + KI) * period_err - KP * LAST_PERIOD_ERR;
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set_adpll(i2c::DCXO::Helper, BASE_ADPLL + adpll)?;
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H_LAST_ADPLL = adpll;
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LAST_PERIOD_ERR = period_err;
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@ -532,7 +530,7 @@ pub mod wrpll {
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let phase_err = tag_collector::get_phase_error();
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unsafe {
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// Based on https://hackmd.io/IACbwcOTSt6Adj3_F9bKuw?view#Integral-wind-up-and-output-limiting
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let adpll = (M_LAST_ADPLL + (KP + KI) * phase_err - KP * LAST_PHASE_ERR).clamp(-ADPLL_LIM, ADPLL_LIM);
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let adpll = M_LAST_ADPLL + (KP + KI) * phase_err - KP * LAST_PHASE_ERR;
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set_adpll(i2c::DCXO::Main, BASE_ADPLL + adpll)?;
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M_LAST_ADPLL = adpll;
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LAST_PHASE_ERR = phase_err;
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