 Ryan Summers
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2ef27b8187
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Formatting
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2021-01-20 12:55:55 +01:00 |
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Ryan Summers
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b2cbc6791d
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Restructuring
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2021-01-20 12:55:45 +01:00 |
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Ryan Summers
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f1f15aca65
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Refactoring app structure
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2021-01-20 12:49:07 +01:00 |
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Ryan Summers
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a715680482
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Merge branch 'master' into feature/lockin-app-refactor
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2021-01-20 12:36:20 +01:00 |
Ryan Summers
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058e474b78
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Merge pull request #230 from vertigo-designs/feature/hardware-module
Refactoring to support multiple apps
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2021-01-20 12:35:36 +01:00 |
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Ryan Summers
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ac06f811ab
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Adding framework for initial lockin demo
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2021-01-18 18:02:00 +01:00 |
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Ryan Summers
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573189bdd9
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Fixing build
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2021-01-18 17:23:21 +01:00 |
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Ryan Summers
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9d90d7b0d2
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Adding WIP apps
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2021-01-18 17:20:33 +01:00 |
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Ryan Summers
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6618e921fe
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Moving panic configuration
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2021-01-18 16:55:56 +01:00 |
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Ryan Summers
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8dd72ae75e
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Reordering
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2021-01-18 16:52:09 +01:00 |
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Ryan Summers
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20535a721d
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Refactoring to support multiple apps
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2021-01-18 16:47:47 +01:00 |
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Ryan Summers
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d447501c47
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Merge pull request #208 from vertigo-designs/feature/io-docs
Adding documentation, updating DAC output timing
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2021-01-18 13:54:56 +01:00 |
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Ryan Summers
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7a2f950667
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Updating timer compare offsets
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2021-01-18 13:41:23 +01:00 |
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Ryan Summers
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598a48b178
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Merge branch 'master' into feature/io-docs
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2021-01-18 13:25:03 +01:00 |
 Robert Jördens
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1d0e1f9651
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Merge pull request #222 from matthuszagh/lockin
Lockin
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2021-01-13 18:47:37 +01:00 |
Matt Huszagh
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9697560404
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reciprocal_pll: remove unneeded type cast
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2021-01-13 09:08:16 -08:00 |
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Matt Huszagh
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e599977983
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revert changes in main.rs and server.rs
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2021-01-13 08:59:27 -08:00 |
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Matt Huszagh
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76088efda5
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dsp: add reciprocal_pll
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2021-01-13 08:37:33 -08:00 |
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Matt Huszagh
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6aad92af43
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fix bug in which real signal component is assigned twice
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2021-01-12 18:36:18 -08:00 |
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Matt Huszagh
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07b7201b49
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fix cargo fmt style
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2021-01-12 17:26:42 -08:00 |
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Matt Huszagh
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a0d472b398
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use only integer iir
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2021-01-12 17:21:55 -08:00 |
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Matt Huszagh
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f974f4099c
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remove TODO note relating ADC_BATCHES and calculate_timestamp_timer_period
Having both is not really redundant.
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2021-01-12 16:17:58 -08:00 |
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Matt Huszagh
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80ed715f5a
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shift sin/cos before demodulation product to avoid i64
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2021-01-12 16:07:04 -08:00 |
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Matt Huszagh
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41ea2ebed4
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use round up half integer rounding
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2021-01-12 15:59:03 -08:00 |
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Matt Huszagh
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4c033c0f3e
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move timestamp handling into new TimestampHandler struct
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2021-01-12 13:06:49 -08:00 |
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Matt Huszagh
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e14aa8b613
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move lock-in code to main.rs
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2021-01-12 10:45:34 -08:00 |
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Matt Huszagh
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891aad3f17
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remove debug_assert in divide_round
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2021-01-12 07:43:28 -08:00 |
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Matt Huszagh
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31d23a3e0c
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lock-in: use same method for batch_index branching in both instances
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2021-01-12 07:36:56 -08:00 |
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Matt Huszagh
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bae295140d
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update lock-in for integer math and PLL
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2021-01-12 07:36:56 -08:00 |
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Matt Huszagh
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028f4a1bb2
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fix small typos
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2021-01-12 07:36:56 -08:00 |
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Ryan Summers
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ad3681f30b
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Merge pull request #223 from quartiq/rs/issue-219/adc-setup
Conforming to external ADC conversion timing
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2021-01-12 07:05:17 -08:00 |
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Ryan Summers
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db3a42a7b9
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Update src/adc.rs
Co-authored-by: Robert Jördens <rj@quartiq.de>
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2021-01-12 06:54:16 -08:00 |
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Ryan Summers
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bcf7a59993
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Removing dac isr clear
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2021-01-12 14:15:45 +01:00 |
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Ryan Summers
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09ecd3291a
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Merge branch 'rs/issue-219/adc-setup' into feature/io-docs
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2021-01-12 14:02:19 +01:00 |
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Ryan Summers
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6b170c25ed
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Fixing timing synchronization
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2021-01-12 13:29:15 +01:00 |
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Ryan Summers
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91975993cf
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Fixing docs
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2021-01-11 12:38:20 +01:00 |
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Ryan Summers
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d5c21efc9d
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Adding extra DMA transfer to clear TXTF in ADC SPI transfers
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2021-01-11 12:31:15 +01:00 |
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Ryan Summers
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1307ddb0ba
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Merge pull request #196 from vertigo-designs/feature/pounder-timestamping
Feature/pounder timestamping
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2021-01-11 01:50:09 -08:00 |
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Robert Jördens
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f785ec2f51
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hitl: dispatch stabilizer event
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2021-01-08 19:13:48 +01:00 |
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Robert Jördens
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09a7ab2773
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ci: correctly use stable toolchain
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2021-01-08 19:09:42 +01:00 |
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Robert Jördens
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96dc13da35
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hitl: rename, add badge
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2021-01-08 19:05:51 +01:00 |
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Robert Jördens
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5ecb28fb05
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Merge pull request #220 from quartiq/jordens-hitl
hardware in the loop testing
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2021-01-08 17:30:12 +01:00 |
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Robert Jördens
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72d69960ca
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Create hitl.yml
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2021-01-08 17:28:07 +01:00 |
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Ryan Summers
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5eab732d93
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Adding information about DSP timing specifications
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2021-01-06 15:38:04 +01:00 |
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Ryan Summers
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56366a013f
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Specifying consequences of failing to meet timing
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2021-01-06 15:34:12 +01:00 |
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Ryan Summers
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f6062c666e
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Fixing pounder v1.1 build
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2021-01-06 15:13:28 +01:00 |
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Ryan Summers
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4b3ceb0c0b
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Merge branch 'feature/io-docs' of github.com:vertigo-designs/stabilizer into feature/io-docs
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2021-01-06 15:12:25 +01:00 |
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Ryan Summers
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eefb2acfda
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Updating dependencies
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2021-01-06 15:12:03 +01:00 |
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Ryan Summers
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cd4721b506
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Merge branch 'master' into feature/io-docs
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2021-01-06 15:10:30 +01:00 |
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Ryan Summers
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f825f52785
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Apply suggestions from code review
Co-authored-by: Robert Jördens <rj@quartiq.de>
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2021-01-06 06:08:07 -08:00 |