Update src/adc.rs
Co-authored-by: Robert Jördens <rj@quartiq.de>
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///! Stabilizer ADC management interface
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///!
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///! The Stabilizer ADCs utilize three DMA channels: one to trigger sampling, one to collect
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///! The Stabilizer ADCs utilize three DMA channels each: one to trigger sampling, one to collect
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///! samples, and one to clear the EOT flag betwen samples. The SPI interfaces are configured
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///! for receiver-only operation. A timer channel is
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///! configured to generate a DMA write into the SPI CR1 register, which initiates a SPI transfer and
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