Restructuring
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@ -75,11 +75,3 @@ opt-level = 3
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debug = true
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lto = true
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codegen-units = 1
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[[bin]]
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name = "iir"
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path = "src/iir.rs"
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[[bin]]
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name = "lockin"
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path = "src/lockin.rs"
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@ -12,21 +12,13 @@ use rtic::cyccnt::{Instant, U32Ext};
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use heapless::{consts::*, String};
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// The number of ticks in the ADC sampling timer. The timer runs at 100MHz, so the step size is
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// equal to 10ns per tick.
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// Currently, the sample rate is equal to: Fsample = 100/256 MHz = 390.625 KHz
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const ADC_SAMPLE_TICKS: u16 = 256;
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// The desired ADC sample processing buffer size.
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const SAMPLE_BUFFER_SIZE: usize = 8;
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// A constant sinusoid to send on the DAC output.
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const DAC_SEQUENCE: [f32; 8] = [0.0, 0.707, 1.0, 0.707, 0.0, -0.707, -1.0, -0.707];
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#[macro_use]
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mod server;
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mod hardware;
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use hardware::{Adc1Input, Dac0Output, Dac1Output, AFE0, AFE1};
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use stabilizer::{
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hardware::{self, Adc1Input, Dac0Output, Dac1Output, AFE0, AFE1},
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server
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};
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use dsp::iir;
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const SCALE: f32 = ((1 << 15) - 1) as f32;
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@ -166,7 +158,7 @@ const APP: () = {
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} else {
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server.poll(socket, |req| {
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info!("Got request: {:?}", req);
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route_request!(req,
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stabilizer::route_request!(req,
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readable_attributes: [
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"stabilizer/iir/state": (|| {
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let state = c.resources.iir_state.lock(|iir_state|
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