Fixing docs
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src/adc.rs
12
src/adc.rs
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///! Stabilizer ADC management interface
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///!
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///! The Stabilizer ADCs utilize a DMA channel to trigger sampling. The SPI streams are configured
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///! for full-duplex operation, but only RX is connected to physical pins. A timer channel is
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///! configured to generate a DMA write into the SPI TXFIFO, which initiates a SPI transfer and
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///! results in an ADC sample read for both channels.
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///! The Stabilizer ADCs utilize three DMA channels: one to trigger sampling, one to collect
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///! samples, and one to clear the TXTF flag betwen samples. The SPI interfaces are configured
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///! for receiver-only operation. A timer channel is
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///! configured to generate a DMA write into the SPI CR1 register, which initiates a SPI transfer and
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///! results in a single ADC sample read for both channels. A separate timer channel is configured to
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///! occur immediately before the trigger channel, which initiates a write to the IFCR (flag-clear)
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///! register to clear the TXTF flag, which allows for a new transmission to be generated by the
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///! trigger channel.
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///!
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///! In order to read multiple samples without interrupting the CPU, a separate DMA transfer is
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///! configured to read from each of the ADC SPI RX FIFOs. Due to the design of the SPI peripheral,
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