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# riscv-formal-nmigen
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A port of [riscv-formal ](https://github.com/SymbioticEDA/riscv-formal ) to nMigen
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## Breakdown
| Directory | Description |
| --- | --- |
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| `shell.nix` | [nix-shell ](https://nixos.wiki/wiki/Development_environment_with_nix-shell ) configuration file |
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| `rvfi` | RISC-V Formal Verification Framework (nMigen port) |
| `rvfi/insns` | Supported RISC-V instructions and ISAs |
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| `rvfi/cores` | Example cores for verification with riscv-formal-nmigen |
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| `rvfi/cores/minerva` | The [Minerva ](https://github.com/lambdaconcept/minerva ) core |
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## Running the Verification
First make sure you have [Nix ](https://nixos.org/download.html ) installed. Then `cd` to the root directory of this repo and run:
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```bash
$ nix-shell
```
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This should give you an environment with all the dependencies required for this project. Then, to run the verification:
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```bash
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$ python -m rvfi.cores.minerva.verify
```
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You may see some warnings on unused `Elaboratable` s and deprecated use of `Simulator` emitted which can be safely ignored.
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## Scope
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Support for the RV32I base ISA and RV32M extension are planned and well underway. Support for other ISAs in the original riscv-formal such as RV32C and their 64-bit counterparts may also be added in the future as time permits.
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## License
See [LICENSE ](./LICENSE )