riscv-formal-nmigen/README.md

# riscv-formal-nmigen

A port of [riscv-formal](https://github.com/SymbioticEDA/riscv-formal) to nMigen

## Dependencies

- [nMigen](https://github.com/m-labs/nmigen)
  
  Note that:
  
  1. Even though this project includes a copy of nMigen, it is highly recommended to remove the copy and install the latest version of nMigen on your system for building this repo
  1. The nMigen package that comes with the [Nix](https://nixos.org/features.html) package manager may not contain the latest changes and therefore may not work with this repo
  1. If you do choose to keep the copy of nMigen provided in this repo anyway, you may need to separately install its dependencies for the build to work:
     - [setuptools](https://pypi.org/project/setuptools/)
     - [pyvcd](https://pypi.org/project/pyvcd/)
- [Yosys](https://github.com/YosysHQ/yosys)
- [SymbiYosys](https://github.com/YosysHQ/SymbiYosys)

## Breakdown

| Directory | Description |
| --- | --- |
| `nmigen` | [nMigen](https://github.com/m-labs/nmigen) |
| `rvfi` | RISC-V Formal Verification Framework (nMigen port) |
| `rvfi/insns` | Supported RISC-V instructions and ISAs |
| `rvfi/cores` | Example cores for verification with riscv-formal-nmigen |
| `rvfi/cores/minerva` | The [Minerva](https://github.com/lambdaconcept/minerva) core |

## Build

### Minerva

`cd` to the root directory of this project and do:

```python
$ python -m rvfi.cores.minerva.verify
```

You may see some warning messages about unused `Elaboratable`s and deprecated use of `Simulation` which can be safely ignored.

## Scope

Support for the RV32I base ISA and RV32M extension are planned and well underway. Support for other ISAs in the original riscv-formal such as RV32C and their 64-bit counterparts may also be added in the future as time permits.

## License

See [LICENSE](./LICENSE)