riscv-formal-nmigen/README.md

# riscv-formal-nmigen

A port of [riscv-formal](https://github.com/SymbioticEDA/riscv-formal) to nMigen

## Dependencies

- [nMigen](https://github.com/m-labs/nmigen)

## Breakdown

_This section is currently a work in progress._

| Directory | Description |
| --- | --- |
| `insns` | Supported RISC-V instructions and ISAs |
| `cores` | Example cores to be integrated with riscv-formal-nmigen (WIP) |

## Build

This framework is not ready to be used to verify RISC-V compliant cores at the time of writing. Instructions for running the framework against such a core will be added once the framework is ready for use.

## Scope

Support for the RV32I base ISA and RV32M extension are planned and well underway. Support for other ISAs in the original riscv-formal such as RV32C and their 64-bit counterparts may also be added in the future as time permits.

## License

See [LICENSE](./LICENSE)
Initial commit 2020-07-14 10:30:37 +08:00			`# riscv-formal-nmigen`

Copy license from source 2020-07-14 10:42:06 +08:00			`A port of [riscv-formal](https://github.com/SymbioticEDA/riscv-formal) to nMigen`
Add LUI instruction for RV32I 2020-07-21 16:13:52 +08:00
			`## Dependencies`

			`- [nMigen](https://github.com/m-labs/nmigen)`

Add Minerva core, to be integrated later 2020-08-13 17:38:04 +08:00			`## Breakdown`

			`_This section is currently a work in progress._`

			`\| Directory \| Description \|`
			`\| --- \| --- \|`
			\| `insns` \| Supported RISC-V instructions and ISAs \|
			\| `cores` \| Example cores to be integrated with riscv-formal-nmigen (WIP) \|

Add LUI instruction for RV32I 2020-07-21 16:13:52 +08:00			`## Build`

Add Minerva core, to be integrated later 2020-08-13 17:38:04 +08:00			`This framework is not ready to be used to verify RISC-V compliant cores at the time of writing. Instructions for running the framework against such a core will be added once the framework is ready for use.`
Add LUI instruction for RV32I 2020-07-21 16:13:52 +08:00
Add README for instructions 2020-08-05 12:54:46 +08:00			`## Scope`
Mention expected scope of project in README 2020-07-21 17:55:28 +08:00
Add Minerva core, to be integrated later 2020-08-13 17:38:04 +08:00			`Support for the RV32I base ISA and RV32M extension are planned and well underway. Support for other ISAs in the original riscv-formal such as RV32C and their 64-bit counterparts may also be added in the future as time permits.`
Mention expected scope of project in README 2020-07-21 17:55:28 +08:00
Add LUI instruction for RV32I 2020-07-21 16:13:52 +08:00			`## License`

			`See [LICENSE](./LICENSE)`