# riscv-formal-nmigen

A port of [riscv-formal](https://github.com/SymbioticEDA/riscv-formal) to nMigen

## Breakdown

| Directory | Description |
| --- | --- |
| `shell.nix` | [nix-shell](https://nixos.wiki/wiki/Development_environment_with_nix-shell) configuration file |
| `rvfi` | RISC-V Formal Verification Framework (nMigen port) |
| `rvfi/insns` | Supported RISC-V instructions and ISAs |
| `rvfi/cores` | Example cores for verification with riscv-formal-nmigen |
| `rvfi/cores/minerva` | The [Minerva](https://github.com/lambdaconcept/minerva) core |

## Running the Verification

First make sure you have [Nix](https://nixos.org/download.html) installed. Then `cd` to the root directory of this repo and run:

```bash
$ nix-shell
```

This should give you an environment with all the dependencies required for this project. Then, to run the verification:

```bash
$ python -m rvfi.cores.minerva.verify
```

You may see some warnings on unused `Elaboratable`s and deprecated use of `Simulator` emitted which can be safely ignored.

## Scope

Support for the RV32I base ISA and RV32M extension are planned and well underway. Support for other ISAs in the original riscv-formal such as RV32C and their 64-bit counterparts may also be added in the future as time permits.

## License

See [LICENSE](./LICENSE)