Mention expected scope of project in README

2020-07-21 17:55:28 +08:00 · 2020-07-21 17:55:28 +08:00 · 395f29cf93
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@ -10,6 +10,10 @@ A port of [riscv-formal](https://github.com/SymbioticEDA/riscv-formal) to nMigen

 TODO

+## Support
+
+The full [RISC-V specification](https://riscv.org/specifications/) is hundreds of pages long including numerous possible extensions, some of which are still under active development at the time of writing. Therefore, this project does not aim to formalize the entire specification, but only the core parts of the specification, namely RV32I and perhaps RV32IM. Support for other extensions of the RISC-V specification may be added in the future.
+
 ## License

 See [LICENSE](./LICENSE)