Drew
40370c4d45
Docs: fix build warnings ( #1234 )
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* ad9910: finish CONT_RECIRCULATE -> CONT_RAMPUP
Found while building docs. Forgot to refactor strings.
Signed-off-by: Drew Risinger <drewrisinger@users.noreply.github.com>
* spi2: reformat update_xfer_duration_mu docstring
update_xfer_duration_mu docstring threw warning while building docs,
didn't use consistent indent in warning.
Signed-off-by: Drew Risinger <drewrisinger@users.noreply.github.com>
2019-01-09 11:39:23 +08:00
David Nadlinger
4fb434674d
coredevice: Fix ad9910 __all__ exports
2019-01-08 18:55:26 +00:00
0d3e7ba805
nix: add zlib in artiq-dev
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Needed by the Vivado installer.
2019-01-08 20:47:09 +08:00
887cb110a7
firmware: fix default DRTIO routing table
2019-01-08 20:46:53 +08:00
David Nadlinger
cadde970e1
urukul: Expand CPLD sync_sel explanation [nfc]
2019-01-08 02:37:58 +00:00
David Nadlinger
7bcdeb825b
ad9910: Add inverse FTW/ASF conversions
2019-01-08 02:18:14 +00:00
David Nadlinger
4d793d7149
ad9910: Truncate phase word to 16 bits
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This avoids overflowing into the asf portion of the register.
2019-01-08 02:18:14 +00:00
332bd6090f
satman: wait for CPLL/QPLL lock after setting drtio_transceiver::stable_clkin
2019-01-07 17:09:19 +08:00
3217488824
add Sayma RTM DRTIO target
2019-01-07 00:13:47 +08:00
b5501aaf00
firmware: program I2C switch on Sayma RTM
2019-01-06 14:54:52 +08:00
66b3132c28
sayma_amc: fix RTIO TSC instantiation
2019-01-06 14:54:32 +08:00
6e43c41103
firmware: support building without SDRAM
2019-01-05 23:41:30 +08:00
cf9447ab77
rtio/cri: remove unneeded CSR management
2019-01-05 23:40:45 +08:00
2c3510497b
firmware: fix not(has_spiflash) build
2019-01-05 23:40:03 +08:00
d6fea22174
manual: update firmware/gateware build/flashing instructions. Closes #1223
2019-01-05 12:38:54 +08:00
2100a8b1f1
sayma_amc: more fighting with vivado timing analyzer
2019-01-05 12:25:30 +08:00
Drew
94cdad6c1d
artiq_flash: change docs from old -m arg to -V ( #1224 ) ( #1227 )
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`-m` argument is deprecated. Changed to newer `-V` argument
Closes #1224
Signed-off-by: Drew Risinger <drewrisinger@users.noreply.github.com>
2019-01-05 10:22:12 +08:00
Drew Risinger
b58d59a9e7
pyon: fix grammar in module docstring.
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Signed-off-by: Drew Risinger <drewrisinger@users.noreply.github.com>
2019-01-04 19:31:08 +00:00
Drew
3e5cea5d89
Docs: instructions to check if in plugdev group
2019-01-04 19:30:13 +00:00
a93fdb8c9d
drtio: disable all destinations in gateware at startup
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Otherwise, kernels fail to get a RTIODestinationUnreachable exception when attempting
to reach a DRTIO destination that has never been up.
2019-01-04 23:42:12 +08:00
62d7c89c48
sayma_amc: use high-resolution TTL on SMAs ( #792 )
2019-01-03 20:50:38 +08:00
0972d61e81
ttl_serdes_ultrascale: use GTH clock domains
2019-01-03 20:50:04 +08:00
f007895fad
drtio/gth_ultrascale: fix rtiox clock domain
2019-01-03 20:49:38 +08:00
10ebf63c47
jesd204_tools: get the Vivado timing analyzer to behave
2019-01-03 20:22:35 +08:00
d6a3172a3e
update copyright year
2019-01-03 20:21:34 +08:00
4af8fd6a0d
ttl_serdes_ultrascale: fix Input
2019-01-03 20:14:54 +08:00
175f8b8ccc
drtio/gth_ultrascale: generate multiplied RTIO clock from BUFG_GT ( #792 )
2019-01-03 20:14:18 +08:00
77126ce5b3
kasli: use hwrev 1.1 by default for DRTIO examples
2019-01-02 23:04:20 +08:00
ab9ca0ee0a
kasli: use 150MHz for DRTIO by default (Sayma compatibility)
2019-01-02 23:03:57 +08:00
cc58318500
siphaser: autocalibrate skew using RX synchronizer
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* removes the hardcoded, (poorly) manually determined skew value
* does not need si5324_clkout_fabric anymore (broken on Sayma RTM due to wrong IO voltage)
2019-01-02 22:29:27 +08:00
f5cda3689e
sayma_amc: enable DRTIO on master SATA connector for MasterDAC variant
2019-01-02 16:46:16 +08:00
e85df13127
nix: update docs
2019-01-02 16:34:29 +08:00
ec52a1003d
nix: add jesd204b
2019-01-02 16:34:11 +08:00
d42d607547
nix: add microscope
2019-01-02 16:13:08 +08:00
7a6bdcb041
nix: fix m-labs URLs
2019-01-02 16:04:25 +08:00
48793b7ecf
nix: reorganize .nix files
2019-01-01 23:39:38 +08:00
e2799803cb
nix: do not install development packages in user environment
2019-01-01 23:35:55 +08:00
1e7ba3227f
nix: add development environment
2019-01-01 22:26:32 +08:00
421ad9c916
nix: bump llvmlite
2018-12-22 14:01:52 +08:00
e80d80f133
manual: move to correct directory for building rust crates. Closes #1222
2018-12-21 10:37:08 +08:00
Drew
d60b95f481
tdr.py: typo ( #1220 )
2018-12-18 18:47:09 +00:00
a7d4d3bda9
ad9910: CONT_RECIRCULATE -> CONT_RAMPUP
2018-12-17 13:25:00 +00:00
35bdf26f01
Merge branch 'ad9910-ram'
2018-12-17 21:16:44 +08:00
David Nadlinger
e608d6ffd3
coredevice, firmware: Add rtio_input_timestamped_data
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Integration tests to follow as part of an RTIO counter phy that
makes use of this.
2018-12-15 00:35:04 +00:00
David Nadlinger
8e30c4574b
firmware: Treat timestamps consistently as signed [nfc]
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This matches other functions and the ARTIQ Python side, but
isn't actually an ABI change.
2018-12-15 00:02:18 +00:00
38ce7ab8ff
sync_struct: handle TimeoutError as subscriber disconnection. Closes #1215
2018-12-13 06:58:54 +08:00
c09ab8502c
nix: cleanup
2018-12-13 06:57:10 +08:00
Joachim Schiele
73941d4661
nix: add rustc, migen and misoc
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This allows firmware compilation.
2018-12-12 22:24:55 +00:00
79eadb9465
ad9910: add RAM mode methods
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* also refactor the CFR1 access into a method
c.f. #1154
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-12-11 14:54:16 +00:00
6df4ae934f
eem: name the servo submodule
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This allows the migen namer to derive names for the ADC return clock
domain in the case of multiple SUServos
close #1201
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-12-11 11:36:40 +01:00
