M-Labs
/
artiq
mirror of https://github.com/m-labs/artiq
2
0
Fork 1
Code Issues Projects Releases Wiki Activity

ad9910: Truncate phase word to 16 bits 

This avoids overflowing into the asf portion of the register.
pull/1231/head
David Nadlinger 2019-01-08 02:08:13 +00:00
parent 332bd6090f
commit 4d793d7149
1 changed files with 2 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
artiq/coredevice/ad9910.py
View File

@ -415,7 +415,8 @@ class AD9910:
# is equivalent to an output pipeline latency.
dt = int32(now_mu()) - int32(ref_time)
pow_ += dt*ftw*self.sysclk_per_mu >> 16
self.write64(_AD9910_REG_PROFILE0 + profile, (asf << 16) | pow_, ftw)
self.write64(_AD9910_REG_PROFILE0 + profile,
(asf << 16) | (pow_ & 0xffff), ftw)
delay_mu(int64(self.io_update_delay))
self.cpld.io_update.pulse_mu(8) # assumes 8 mu > t_SYSCLK
at_mu(now_mu() & ~0xf)