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satman: wait for CPLL/QPLL lock after setting drtio_transceiver::stable_clkin
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@ -416,6 +416,7 @@ pub extern fn main() -> i32 {
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unsafe {
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csr::drtio_transceiver::stable_clkin_write(1);
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}
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clock::spin_us(1500); // wait for CPLL/QPLL lock
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init_rtio_crg();
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#[cfg(has_allaki_atts)]
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