tdr.py: typo (#1220)

2018-12-18 13:47:09 -05:00 · 2018-12-18 13:47:09 -05:00 · d60b95f481
parent a7d4d3bda9
commit d60b95f481
1 changed files with 1 additions and 1 deletions
--- a/artiq/examples/kc705_nist_clock/repository/tdr.py
+++ b/artiq/examples/kc705_nist_clock/repository/tdr.py
@ -44,7 +44,7 @@ class TDR(EnvExperiment):
        try:
            self.many(n, self.core.seconds_to_mu(pulse))
        except PulseNotReceivedError:
-            print("to few edges: cable too long or wiring bad")
+            print("too few edges: cable too long or wiring bad")
        else:
            print(self.t)
            t_rise = mu_to_seconds(self.t[0], self.core)/n - latency