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3651 Commits

Author SHA1 Message Date
Robert Jördens cccd01e81e sawg: cleanup sat_add logic 2017-06-22 10:26:29 +02:00
Robert Jördens 5f6e665158 test/sawg: patch delay_mu 2017-06-22 10:26:29 +02:00
Robert Jördens 570f2cc1ff dsp/tools/SatAdd: fix reuse of clipped signal 2017-06-22 10:26:29 +02:00
Robert Jördens 4b3aad2563 sawg: clean up Config 
* unify I and Q data limiters. there is no conceivable way why they
would be different.
* reorder clr bits to be like consistent
* move the sat add limiter to before the hbf again
 2017-06-22 10:26:29 +02:00
Robert Jördens f4c6879c76 sawg: special case Config RTIO address 2017-06-22 10:26:29 +02:00
Robert Jördens ff0da2c9fc sawg: stage code for y-data exchange on channels 2017-06-22 10:26:29 +02:00
Robert Jördens b6569df02f dsp/tools: clean up SatAddMixin logic 2017-06-22 10:26:29 +02:00
Robert Jördens f369cb97f7 sawg/examples: add a bit more slack 2017-06-22 10:26:29 +02:00
Chris Ballance 05b57f5110 protocols: increase another asyncio line limit (#671) 2017-06-22 09:43:52 +08:00
Sebastien Bourdeauducq c2cc29142d drtio: remove misleading comment from device_db 2017-06-21 18:34:53 +08:00
Sebastien Bourdeauducq 6262969d46 test: relax test_dma_record_time 2017-06-21 18:33:58 +08:00
Sebastien Bourdeauducq 64ce85445c drtio: add remote converter SPI example (#740) 2017-06-21 17:08:12 +08:00
Sebastien Bourdeauducq 74cf074538 drtio: remove sawg_3g from example targets, add converter SPI bus from FMC-EBZ at all times 2017-06-21 17:01:52 +08:00
Sebastien Bourdeauducq 66dee9d1ad drtio: send/process I2C and SPI aux packets (#740) 2017-06-21 16:50:51 +08:00
Sebastien Bourdeauducq f58f16ccd4 drtioaux: add default timeout 2017-06-21 16:23:11 +08:00
Sebastien Bourdeauducq 7675dd063b drtioaux: add I2C and SPI packets (#740) 2017-06-21 14:07:16 +08:00
Sebastien Bourdeauducq c74de6ae96 phaser: reintroduce test_ad9154_status 2017-06-20 00:49:57 +08:00
Sebastien Bourdeauducq 8c56a95fa2 spi: add default busno 2017-06-20 00:49:38 +08:00
Sebastien Bourdeauducq 39ddb66f0f phaser: add AD9154 SPI access driver to example ddb 2017-06-20 00:49:21 +08:00
Sebastien Bourdeauducq 470bce6214 coredevice: add AD9154 SPI access driver 2017-06-20 00:48:50 +08:00
Sebastien Bourdeauducq a6d06824e7 fix indentation 2017-06-20 00:12:11 +08:00
Sebastien Bourdeauducq 8f2d85fc5b add back ad9154_reg.py 2017-06-19 23:45:32 +08:00
Sebastien Bourdeauducq c86029bca2 i2c: expose restart as syscall, add structure for I2C-over-DRTIO 2017-06-19 23:44:51 +08:00
Sebastien Bourdeauducq 268b7d8aaf typo 2017-06-19 15:42:10 +08:00
Sebastien Bourdeauducq 09d198c7a1 test: add test for exception on non-existent I2C bus 2017-06-19 15:32:09 +08:00
Sebastien Bourdeauducq d08bd58dff versioneer: cut git hashes consistently (#753) 2017-06-19 15:31:48 +08:00
Sebastien Bourdeauducq 6c6bb67618 libboard: fix compiler warning on not(has_i2c) 2017-06-19 14:57:15 +08:00
Sebastien Bourdeauducq 5d63489080 i2c,spi: add busno error detection 2017-06-19 14:27:30 +08:00
Robert Jördens 0d8067256b rtio: refactor RelaxedAsyncResetSynchronizer 2017-06-18 14:37:08 +02:00
Sebastien Bourdeauducq 8399f8893d add kernel access to non-realtime SPI buses (#740) 2017-06-18 12:45:07 +08:00
Robert Jördens 424b2bfbd8 rtio: describe rio and rio_phy domains a bit more 2017-06-17 12:21:07 +02:00
Robert Jördens 219dfd8984 rtio: add one register level for rio and rio_phy resets 
* This should give Vivado some wiggle room during PnR.
* It needs three new clock domains which is ugly. But since
AsyncResetSynchronizer can only drive clock domains resets directly
there seems to be no other way to add one register level currently.
 2017-06-17 12:17:48 +02:00
Sebastien Bourdeauducq 8fea361412 firmware: always use 8 characters to abbreviate git commit hashes 2017-06-17 14:43:50 +08:00
Robert Jördens e19bfd4781 test_sawg_fe: add ref_multiplier to simulated core 2017-06-16 19:45:24 +02:00
Robert Jördens b5772f478a sawg: add channel reset (closes #751) 2017-06-16 19:31:57 +02:00
Robert Jördens 2a76034fbc cri: add note about clearing of o_data 2017-06-16 19:06:00 +02:00
Robert Jördens fecc42fd0c sawg/phaser: expand documentation (closes #750) 2017-06-14 11:49:52 +02:00
Robert Jördens 858c1be381 sawg: expand documentation 2017-06-13 18:51:48 +02:00
Robert Jördens 3f37870e25 sawg: register pre-hbf adder 2017-06-13 18:15:44 +02:00
Robert Jördens e229edd5d5 sawg: add register after hbf for timing 2017-06-12 23:08:27 +02:00
Robert Jördens 315338fca9 test/sawg: test HBF overshoot, fix sim patching 2017-06-12 20:35:47 +02:00
Robert Jördens 9a8a7b9102 sawg: handle clipping interpolator 
* give 1 bit headroom to interpolator to handle overshoot
* fix Config limiter widths (NFC)
* move clipper to behind the HBF to correctly shield DUC

This leaves a factor of two headroom for the sum of the following
effects:

  * HBF overshoot (~15 % of the step)
  * A1/A2 DDS sum

While this is technically not sufficient and can still lead to
overflows, it is unlikely that one would trigger those. It would require
doing large amplitude A1, large amplitude A2 and additionally doing
amplitude/phase jumps that would overshoot the HBF. No sane person would
try that, right?

closes #743
 2017-06-12 20:33:54 +02:00
Robert Jördens 1fb3995ffc Revert "fir/ParallelHBFUpsampler: add headroom (gain=2)" 
This reverts commit 6ac9d0c41e.

Overshooting behavior must to be handled outside the FIR.
 2017-06-12 20:07:25 +02:00
Robert Jördens 332bcc7f3b fir: check widths 2017-06-12 20:07:23 +02:00
Robert Jördens 39a1dcbb3d test/fir: look at overshoot behavior 2017-06-12 20:06:07 +02:00
Robert Jördens 6ac9d0c41e fir/ParallelHBFUpsampler: add headroom (gain=2) 
This addresses part of #743
 2017-06-12 18:59:45 +02:00
Robert Jördens 566ff73dff pdq: unify spi-PDQ and usb-PDQ protocols 2017-06-10 15:03:25 +02:00
Robert Jördens 6c54c0f834 sawg: update example 2017-06-10 11:52:48 +02:00
Robert Jördens d8aee931ba sawg: extend phase mode docs 2017-06-09 12:26:49 +02:00
whitequark f7254dd3ce compiler.validators.constness: take AugAssign into account. 2017-06-09 07:31:08 +00:00