mirror of
https://github.com/m-labs/artiq.git
synced 2024-12-25 03:08:27 +08:00
add kernel access to non-realtime SPI buses (#740)
This commit is contained in:
parent
424b2bfbd8
commit
8399f8893d
@ -30,6 +30,9 @@ def i2c_read(busno: TInt32, ack: TBool) -> TInt32:
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class PCA9548:
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"""Driver for the PCA9548 I2C bus switch.
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I2C transactions not real-time, and are performed by the CPU without
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involving RTIO.
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On the KC705, this chip is used for selecting the I2C buses on the two FMC
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connectors. HPC=1, LPC=2.
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"""
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@ -72,6 +75,9 @@ class PCA9548:
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class TCA6424A:
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"""Driver for the TCA6424A I2C I/O expander.
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I2C transactions not real-time, and are performed by the CPU without
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involving RTIO.
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On the NIST QC2 hardware, this chip is used for switching the directions
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of TTL buffers."""
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def __init__(self, dmgr, busno=0, address=0x44, core_device="core"):
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@ -1,10 +1,20 @@
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import numpy
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from artiq.language.core import kernel, portable, now_mu, delay_mu
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from artiq.language.core import syscall, kernel, portable, now_mu, delay_mu
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from artiq.language.types import TInt32, TNone
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from artiq.language.units import MHz
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from artiq.coredevice.rtio import rtio_output, rtio_input_data
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__all__ = [
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"SPI_DATA_ADDR", "SPI_XFER_ADDR", "SPI_CONFIG_ADDR",
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"SPI_OFFLINE", "SPI_ACTIVE", "SPI_PENDING",
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"SPI_CS_POLARITY", "SPI_CLK_POLARITY", "SPI_CLK_PHASE",
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"SPI_LSB_FIRST", "SPI_HALF_DUPLEX",
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"SPIMaster", "NRTSPIMaster"
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]
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SPI_DATA_ADDR, SPI_XFER_ADDR, SPI_CONFIG_ADDR = range(3)
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(
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SPI_OFFLINE,
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@ -262,3 +272,65 @@ class SPIMaster:
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rtio_output(now_mu(), self.channel, SPI_CONFIG_ADDR | SPI_RT2WB_READ,
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0)
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return rtio_input_data(self.channel)
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@syscall(flags={"nounwind", "nowrite"})
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def spi_set_config(busno: TInt32, flags: TInt32, write_div: TInt32, read_div: TInt32) -> TNone:
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raise NotImplementedError("syscall not simulated")
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@syscall(flags={"nounwind", "nowrite"})
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def spi_set_xfer(busno: TInt32, chip_select: TInt32, write_length: TInt32, read_length: TInt32) -> TNone:
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raise NotImplementedError("syscall not simulated")
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@syscall(flags={"nounwind", "nowrite"})
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def spi_write(busno: TInt32, data: TInt32) -> TNone:
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raise NotImplementedError("syscall not simulated")
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@syscall(flags={"nounwind", "nowrite"})
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def spi_read(busno: TInt32) -> TInt32:
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raise NotImplementedError("syscall not simulated")
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class NRTSPIMaster:
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"""Core device non-realtime Serial Peripheral Interface (SPI) bus master.
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Owns one non-realtime SPI bus.
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With this driver, SPI transactions and are performed by the CPU without
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involving RTIO.
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Realtime and non-realtime buses are separate and defined at bitstream
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compilation time.
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See :class:`SPIMaster` for a description of the methods.
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"""
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def __init__(self, dmgr, busno, core_device="core"):
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self.core = dmgr.get(core_device)
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self.busno = busno
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@kernel
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def set_config_mu(self, flags=0, write_div=6, read_div=6):
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"""Set the ``config`` register.
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Note that the non-realtime SPI cores are usually clocked by the system
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clock and not the RTIO clock. In many cases, the SPI configuration is
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already set by the firmware and you do not need to call this method.
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The offline bit cannot be set using this method.
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The SPI bus is briefly taken offline when this method is called.
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"""
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spi_set_config(self.busno, flags, write_div, read_div)
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@kernel
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def set_xfer(self, chip_select=0, write_length=0, read_length=0):
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spi_set_xfer(self.busno, chip_select, write_length, read_length)
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@kernel
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def write(self, data=0):
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spi_write(self.busno, data)
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@kernel
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def read(self):
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return spi_read(self.busno)
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@ -117,8 +117,13 @@ static mut API: &'static [(&'static str, *const ())] = &[
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api!(drtio_get_packet_counts = ::rtio::drtio_dbg::get_packet_counts),
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api!(drtio_get_fifo_space_req_count = ::rtio::drtio_dbg::get_fifo_space_req_count),
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api!(i2c_start = ::i2c_start),
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api!(i2c_stop = ::i2c_stop),
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api!(i2c_write = ::i2c_write),
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api!(i2c_read = ::i2c_read),
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api!(i2c_start = ::nrt_bus::i2c::start),
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api!(i2c_stop = ::nrt_bus::i2c::stop),
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api!(i2c_write = ::nrt_bus::i2c::write),
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api!(i2c_read = ::nrt_bus::i2c::read),
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api!(spi_set_config = ::nrt_bus::spi::set_config),
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api!(spi_set_xfer = ::nrt_bus::spi::set_xfer),
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api!(spi_write = ::nrt_bus::spi::write),
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api!(spi_read = ::nrt_bus::spi::read),
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];
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@ -89,6 +89,7 @@ macro_rules! raise {
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pub mod eh;
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mod api;
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mod rtio;
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mod nrt_bus;
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static mut NOW: u64 = 0;
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static mut LIBRARY: Option<Library<'static>> = None;
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@ -220,24 +221,6 @@ extern fn cache_put(key: CSlice<u8>, list: CSlice<i32>) {
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})
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}
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extern fn i2c_start(busno: i32) {
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send(&I2cStartRequest { busno: busno as u8 });
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}
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extern fn i2c_stop(busno: i32) {
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send(&I2cStopRequest { busno: busno as u8 });
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}
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extern fn i2c_write(busno: i32, data: i32) -> bool {
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send(&I2cWriteRequest { busno: busno as u8, data: data as u8 });
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recv!(&I2cWriteReply { ack } => ack)
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}
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extern fn i2c_read(busno: i32, ack: bool) -> i32 {
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send(&I2cReadRequest { busno: busno as u8, ack: ack });
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recv!(&I2cReadReply { data } => data) as i32
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}
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const DMA_BUFFER_SIZE: usize = 64 * 1024;
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struct DmaRecorder {
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48
artiq/firmware/ksupport/nrt_bus.rs
Normal file
48
artiq/firmware/ksupport/nrt_bus.rs
Normal file
@ -0,0 +1,48 @@
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pub mod i2c {
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use ::send;
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use ::recv;
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use kernel_proto::*;
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pub extern fn start(busno: i32) {
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send(&I2cStartRequest { busno: busno as u8 });
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}
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pub extern fn stop(busno: i32) {
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send(&I2cStopRequest { busno: busno as u8 });
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}
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pub extern fn write(busno: i32, data: i32) -> bool {
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send(&I2cWriteRequest { busno: busno as u8, data: data as u8 });
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recv!(&I2cWriteReply { ack } => ack)
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}
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pub extern fn read(busno: i32, ack: bool) -> i32 {
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send(&I2cReadRequest { busno: busno as u8, ack: ack });
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recv!(&I2cReadReply { data } => data) as i32
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}
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}
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pub mod spi {
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use ::send;
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use ::recv;
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use kernel_proto::*;
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pub extern fn set_config(busno: i32, flags: i32, write_div: i32, read_div: i32) {
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send(&SpiSetConfigRequest { busno: busno as u32, flags: flags as u8,
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write_div: write_div as u8, read_div: read_div as u8 });
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}
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pub extern fn set_xfer(busno: i32, chip_select: i32, write_length: i32, read_length: i32) {
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send(&SpiSetXferRequest { busno: busno as u32, chip_select: chip_select as u16,
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write_length: write_length as u8, read_length: read_length as u8 });
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}
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pub extern fn write(busno: i32, data: i32) {
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send(&SpiWriteRequest { busno: busno as u32, data: data as u32 });
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}
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pub extern fn read(busno: i32) -> i32 {
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send(&SpiReadRequest { busno: busno as u32 });
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recv!(&SpiReadReply { data } => data) as i32
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}
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}
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@ -1,147 +1,171 @@
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use csr;
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use clock;
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fn half_period() { clock::spin_us(100) }
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fn sda_bit(busno: u8) -> u8 { 1 << (2 * busno + 1) }
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fn scl_bit(busno: u8) -> u8 { 1 << (2 * busno) }
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#[cfg(has_i2c)]
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mod io {
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use csr;
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use clock;
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fn sda_i(busno: u8) -> bool {
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unsafe {
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csr::i2c::in_read() & sda_bit(busno) != 0
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}
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}
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fn sda_oe(busno: u8, oe: bool) {
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unsafe {
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let reg = csr::i2c::oe_read();
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let reg = if oe { reg | sda_bit(busno) } else { reg & !sda_bit(busno) };
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csr::i2c::oe_write(reg)
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}
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}
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fn sda_o(busno: u8, o: bool) {
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unsafe {
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let reg = csr::i2c::out_read();
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let reg = if o { reg | sda_bit(busno) } else { reg & !sda_bit(busno) };
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csr::i2c::out_write(reg)
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}
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}
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fn scl_oe(busno: u8, oe: bool) {
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unsafe {
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let reg = csr::i2c::oe_read();
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let reg = if oe { reg | scl_bit(busno) } else { reg & !scl_bit(busno) };
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csr::i2c::oe_write(reg)
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}
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}
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fn scl_o(busno: u8, o: bool) {
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unsafe {
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let reg = csr::i2c::out_read();
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let reg = if o { reg | scl_bit(busno) } else { reg & !scl_bit(busno) };
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csr::i2c::out_write(reg)
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pub fn half_period() { clock::spin_us(100) }
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fn sda_bit(busno: u8) -> u8 { 1 << (2 * busno + 1) }
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fn scl_bit(busno: u8) -> u8 { 1 << (2 * busno) }
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pub fn sda_i(busno: u8) -> bool {
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unsafe {
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csr::i2c::in_read() & sda_bit(busno) != 0
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}
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}
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pub fn sda_oe(busno: u8, oe: bool) {
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unsafe {
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let reg = csr::i2c::oe_read();
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let reg = if oe { reg | sda_bit(busno) } else { reg & !sda_bit(busno) };
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csr::i2c::oe_write(reg)
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}
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}
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pub fn sda_o(busno: u8, o: bool) {
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unsafe {
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let reg = csr::i2c::out_read();
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let reg = if o { reg | sda_bit(busno) } else { reg & !sda_bit(busno) };
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csr::i2c::out_write(reg)
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}
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}
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pub fn scl_oe(busno: u8, oe: bool) {
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unsafe {
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let reg = csr::i2c::oe_read();
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let reg = if oe { reg | scl_bit(busno) } else { reg & !scl_bit(busno) };
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csr::i2c::oe_write(reg)
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}
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}
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pub fn scl_o(busno: u8, o: bool) {
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unsafe {
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let reg = csr::i2c::out_read();
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let reg = if o { reg | scl_bit(busno) } else { reg & !scl_bit(busno) };
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csr::i2c::out_write(reg)
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}
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}
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}
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#[cfg(has_i2c)]
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pub fn init() {
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for busno in 0..csr::CONFIG_I2C_BUS_COUNT {
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let busno = busno as u8;
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// Set SCL as output, and high level
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scl_o(busno, true);
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scl_oe(busno, true);
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io::scl_o(busno, true);
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io::scl_oe(busno, true);
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// Prepare a zero level on SDA so that sda_oe pulls it down
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sda_o(busno, false);
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io::sda_o(busno, false);
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// Release SDA
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sda_oe(busno, false);
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io::sda_oe(busno, false);
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// Check the I2C bus is ready
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half_period();
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half_period();
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if !sda_i(busno) {
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io::half_period();
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io::half_period();
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if !io::sda_i(busno) {
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error!("SDA is stuck low on bus #{}", busno)
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}
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}
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}
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#[cfg(has_i2c)]
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pub fn start(busno: u8) {
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// Set SCL high then SDA low
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scl_o(busno, true);
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half_period();
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sda_oe(busno, true);
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half_period();
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io::scl_o(busno, true);
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io::half_period();
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io::sda_oe(busno, true);
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io::half_period();
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}
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#[cfg(has_i2c)]
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pub fn restart(busno: u8) {
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// Set SCL low then SDA high */
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scl_o(busno, false);
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half_period();
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sda_oe(busno, false);
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half_period();
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io::scl_o(busno, false);
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io::half_period();
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io::sda_oe(busno, false);
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io::half_period();
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// Do a regular start
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start(busno);
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}
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#[cfg(has_i2c)]
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pub fn stop(busno: u8) {
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// First, make sure SCL is low, so that the target releases the SDA line
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scl_o(busno, false);
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half_period();
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io::scl_o(busno, false);
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io::half_period();
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// Set SCL high then SDA high
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sda_oe(busno, true);
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scl_o(busno, true);
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half_period();
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sda_oe(busno, false);
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half_period();
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io::sda_oe(busno, true);
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io::scl_o(busno, true);
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io::half_period();
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io::sda_oe(busno, false);
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io::half_period();
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}
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#[cfg(has_i2c)]
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pub fn write(busno: u8, data: u8) -> bool {
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// MSB first
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for bit in (0..8).rev() {
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// Set SCL low and set our bit on SDA
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scl_o(busno, false);
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sda_oe(busno, data & (1 << bit) == 0);
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half_period();
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io::scl_o(busno, false);
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io::sda_oe(busno, data & (1 << bit) == 0);
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io::half_period();
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// Set SCL high ; data is shifted on the rising edge of SCL
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scl_o(busno, true);
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half_period();
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io::scl_o(busno, true);
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io::half_period();
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}
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// Check ack
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// Set SCL low, then release SDA so that the I2C target can respond
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scl_o(busno, false);
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half_period();
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sda_oe(busno, false);
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io::scl_o(busno, false);
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io::half_period();
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io::sda_oe(busno, false);
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// Set SCL high and check for ack
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scl_o(busno, true);
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half_period();
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io::scl_o(busno, true);
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io::half_period();
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// returns true if acked (I2C target pulled SDA low)
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!sda_i(busno)
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!io::sda_i(busno)
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}
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#[cfg(has_i2c)]
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pub fn read(busno: u8, ack: bool) -> u8 {
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// Set SCL low first, otherwise setting SDA as input may cause a transition
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// on SDA with SCL high which will be interpreted as START/STOP condition.
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scl_o(busno, false);
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half_period(); // make sure SCL has settled low
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sda_oe(busno, false);
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io::scl_o(busno, false);
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io::half_period(); // make sure SCL has settled low
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io::sda_oe(busno, false);
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let mut data: u8 = 0;
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// MSB first
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for bit in (0..8).rev() {
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scl_o(busno, false);
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half_period();
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io::scl_o(busno, false);
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io::half_period();
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// Set SCL high and shift data
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scl_o(busno, true);
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half_period();
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if sda_i(busno) { data |= 1 << bit }
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io::scl_o(busno, true);
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io::half_period();
|
||||
if io::sda_i(busno) { data |= 1 << bit }
|
||||
}
|
||||
// Send ack
|
||||
// Set SCL low and pull SDA low when acking
|
||||
scl_o(busno, false);
|
||||
if ack { sda_oe(busno, true) }
|
||||
half_period();
|
||||
io::scl_o(busno, false);
|
||||
if ack { io::sda_oe(busno, true) }
|
||||
io::half_period();
|
||||
// then set SCL high
|
||||
scl_o(busno, true);
|
||||
half_period();
|
||||
io::scl_o(busno, true);
|
||||
io::half_period();
|
||||
|
||||
data
|
||||
}
|
||||
|
||||
#[cfg(not(has_i2c))]
|
||||
pub fn init() {}
|
||||
#[cfg(not(has_i2c))]
|
||||
pub fn start(_busno: u8) {}
|
||||
#[cfg(not(has_i2c))]
|
||||
pub fn restart(_busno: u8) {}
|
||||
#[cfg(not(has_i2c))]
|
||||
pub fn stop(_busno: u8) {}
|
||||
#[cfg(not(has_i2c))]
|
||||
pub fn write(_busno: u8, _data: u8) -> bool { false }
|
||||
#[cfg(not(has_i2c))]
|
||||
pub fn read(_busno: u8, _ack: bool) { 0xff }
|
||||
|
@ -19,8 +19,9 @@ pub mod uart_console;
|
||||
#[cfg(has_spiflash)]
|
||||
pub mod spiflash;
|
||||
|
||||
#[cfg(has_i2c)]
|
||||
pub mod i2c;
|
||||
pub mod spi;
|
||||
|
||||
#[cfg(has_si5324)]
|
||||
pub mod si5324;
|
||||
|
||||
|
54
artiq/firmware/libboard/spi.rs
Normal file
54
artiq/firmware/libboard/spi.rs
Normal file
@ -0,0 +1,54 @@
|
||||
#[cfg(has_converter_spi)]
|
||||
use csr;
|
||||
|
||||
// Later this module should support other buses than the converter SPI bus,
|
||||
// and add a busno parameter to differentiate them.
|
||||
|
||||
#[cfg(has_converter_spi)]
|
||||
pub fn set_config(flags: u8, write_div: u8, read_div: u8) {
|
||||
unsafe {
|
||||
csr::converter_spi::offline_write(1);
|
||||
csr::converter_spi::cs_polarity_write(flags >> 3 & 1);
|
||||
csr::converter_spi::clk_polarity_write(flags >> 4 & 1);
|
||||
csr::converter_spi::clk_phase_write(flags >> 5 & 1);
|
||||
csr::converter_spi::lsb_first_write(flags >> 6 & 1);
|
||||
csr::converter_spi::half_duplex_write(flags >> 7 & 1);
|
||||
csr::converter_spi::clk_div_write_write(write_div);
|
||||
csr::converter_spi::clk_div_read_write(read_div);
|
||||
csr::converter_spi::offline_write(0);
|
||||
}
|
||||
}
|
||||
|
||||
#[cfg(has_converter_spi)]
|
||||
pub fn set_xfer(chip_select: u16, write_length: u8, read_length: u8) {
|
||||
unsafe {
|
||||
csr::converter_spi::cs_write(chip_select as _);
|
||||
csr::converter_spi::xfer_len_write_write(write_length);
|
||||
csr::converter_spi::xfer_len_read_write(read_length);
|
||||
}
|
||||
}
|
||||
|
||||
#[cfg(has_converter_spi)]
|
||||
pub fn write(data: u32) {
|
||||
unsafe {
|
||||
csr::converter_spi::data_write_write(data);
|
||||
while csr::converter_spi::pending_read() != 0 {}
|
||||
while csr::converter_spi::active_read() != 0 {}
|
||||
}
|
||||
}
|
||||
|
||||
#[cfg(has_converter_spi)]
|
||||
pub fn read() -> u32 {
|
||||
unsafe {
|
||||
csr::converter_spi::data_read_read()
|
||||
}
|
||||
}
|
||||
|
||||
#[cfg(not(has_converter_spi))]
|
||||
pub fn set_config(_flags: u8, _write_div: u8, _read_div: u8) {}
|
||||
#[cfg(not(has_converter_spi))]
|
||||
pub fn set_xfer(_chip_select: u16, _write_length: u8, _read_length: u8) {}
|
||||
#[cfg(not(has_converter_spi))]
|
||||
pub fn write(_data: u32) {}
|
||||
#[cfg(not(has_converter_spi))]
|
||||
pub fn read() -> u32 { 0 }
|
@ -87,6 +87,12 @@ pub enum Message<'a> {
|
||||
I2cReadRequest { busno: u8, ack: bool },
|
||||
I2cReadReply { data: u8 },
|
||||
|
||||
SpiSetConfigRequest { busno: u32, flags: u8, write_div: u8, read_div: u8 },
|
||||
SpiSetXferRequest { busno: u32, chip_select: u16, write_length: u8, read_length: u8 },
|
||||
SpiWriteRequest { busno: u32, data: u32 },
|
||||
SpiReadRequest { busno: u32 },
|
||||
SpiReadReply { data: u32 },
|
||||
|
||||
Log(fmt::Arguments<'a>),
|
||||
LogSlice(&'a str)
|
||||
}
|
||||
|
123
artiq/firmware/runtime/kern_hwreq.rs
Normal file
123
artiq/firmware/runtime/kern_hwreq.rs
Normal file
@ -0,0 +1,123 @@
|
||||
use session::{kern_acknowledge, kern_send};
|
||||
use rtio_mgt;
|
||||
use board;
|
||||
use kernel_proto as kern;
|
||||
use std::io;
|
||||
use sched::Io;
|
||||
|
||||
// TODO
|
||||
mod drtio_spi {
|
||||
pub fn set_config(_busno: u32, _flags: u8, _write_div: u8, _read_div: u8) {}
|
||||
pub fn set_xfer(_busno: u32, _chip_select: u16, _write_length: u8, _read_length: u8) {}
|
||||
pub fn write(_busno: u32, _data: u32) {}
|
||||
pub fn read(_busno: u32) -> u32 { 0 }
|
||||
}
|
||||
|
||||
mod spi {
|
||||
use board;
|
||||
use super::drtio_spi;
|
||||
|
||||
pub fn set_config(busno: u32, flags: u8, write_div: u8, read_div: u8) {
|
||||
let drtio = busno >> 16;
|
||||
if drtio == 0 {
|
||||
board::spi::set_config(flags, write_div, read_div)
|
||||
} else {
|
||||
drtio_spi::set_config(busno, flags, write_div, read_div)
|
||||
}
|
||||
}
|
||||
|
||||
pub fn set_xfer(busno: u32, chip_select: u16, write_length: u8, read_length: u8) {
|
||||
let drtio = busno >> 16;
|
||||
if drtio == 0 {
|
||||
board::spi::set_xfer(chip_select, write_length, read_length)
|
||||
} else {
|
||||
drtio_spi::set_xfer(busno, chip_select, write_length, read_length)
|
||||
}
|
||||
}
|
||||
|
||||
pub fn write(busno: u32, data: u32) {
|
||||
let drtio = busno >> 16;
|
||||
if drtio == 0 {
|
||||
board::spi::write(data)
|
||||
} else {
|
||||
drtio_spi::write(busno, data)
|
||||
}
|
||||
}
|
||||
|
||||
pub fn read(busno: u32) -> u32 {
|
||||
let drtio = busno >> 16;
|
||||
if drtio == 0 {
|
||||
board::spi::read()
|
||||
} else {
|
||||
drtio_spi::read(busno)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
pub fn process_kern_hwreq(io: &Io, request: &kern::Message) -> io::Result<bool> {
|
||||
match request {
|
||||
&kern::RtioInitRequest => {
|
||||
info!("resetting RTIO");
|
||||
rtio_mgt::init_core();
|
||||
kern_acknowledge()
|
||||
}
|
||||
|
||||
&kern::DrtioChannelStateRequest { channel } => {
|
||||
let (fifo_space, last_timestamp) = rtio_mgt::drtio_dbg::get_channel_state(channel);
|
||||
kern_send(io, &kern::DrtioChannelStateReply { fifo_space: fifo_space,
|
||||
last_timestamp: last_timestamp })
|
||||
}
|
||||
&kern::DrtioResetChannelStateRequest { channel } => {
|
||||
rtio_mgt::drtio_dbg::reset_channel_state(channel);
|
||||
kern_acknowledge()
|
||||
}
|
||||
&kern::DrtioGetFifoSpaceRequest { channel } => {
|
||||
rtio_mgt::drtio_dbg::get_fifo_space(channel);
|
||||
kern_acknowledge()
|
||||
}
|
||||
&kern::DrtioPacketCountRequest => {
|
||||
let (tx_cnt, rx_cnt) = rtio_mgt::drtio_dbg::get_packet_counts();
|
||||
kern_send(io, &kern::DrtioPacketCountReply { tx_cnt: tx_cnt, rx_cnt: rx_cnt })
|
||||
}
|
||||
&kern::DrtioFifoSpaceReqCountRequest => {
|
||||
let cnt = rtio_mgt::drtio_dbg::get_fifo_space_req_count();
|
||||
kern_send(io, &kern::DrtioFifoSpaceReqCountReply { cnt: cnt })
|
||||
}
|
||||
|
||||
&kern::I2cStartRequest { busno } => {
|
||||
board::i2c::start(busno);
|
||||
kern_acknowledge()
|
||||
}
|
||||
&kern::I2cStopRequest { busno } => {
|
||||
board::i2c::stop(busno);
|
||||
kern_acknowledge()
|
||||
}
|
||||
&kern::I2cWriteRequest { busno, data } => {
|
||||
let ack = board::i2c::write(busno, data);
|
||||
kern_send(io, &kern::I2cWriteReply { ack: ack })
|
||||
}
|
||||
&kern::I2cReadRequest { busno, ack } => {
|
||||
let data = board::i2c::read(busno, ack);
|
||||
kern_send(io, &kern::I2cReadReply { data: data })
|
||||
},
|
||||
|
||||
&kern::SpiSetConfigRequest { busno, flags, write_div, read_div } => {
|
||||
spi::set_config(busno, flags, write_div, read_div);
|
||||
kern_acknowledge()
|
||||
},
|
||||
&kern::SpiSetXferRequest { busno, chip_select, write_length, read_length } => {
|
||||
spi::set_xfer(busno, chip_select, write_length, read_length);
|
||||
kern_acknowledge()
|
||||
}
|
||||
&kern::SpiWriteRequest { busno, data } => {
|
||||
spi::write(busno, data);
|
||||
kern_acknowledge()
|
||||
}
|
||||
&kern::SpiReadRequest { busno } => {
|
||||
let data = spi::read(busno);
|
||||
kern_send(io, &kern::SpiReadReply { data: data })
|
||||
},
|
||||
|
||||
_ => return Ok(false)
|
||||
}.and(Ok(true))
|
||||
}
|
@ -47,6 +47,7 @@ mod rtio_dma;
|
||||
|
||||
mod mgmt;
|
||||
mod kernel;
|
||||
mod kern_hwreq;
|
||||
mod session;
|
||||
#[cfg(any(has_rtio_moninj, has_drtio))]
|
||||
mod moninj;
|
||||
|
@ -15,6 +15,7 @@ use board;
|
||||
use rpc_proto as rpc;
|
||||
use session_proto as host;
|
||||
use kernel_proto as kern;
|
||||
use kern_hwreq;
|
||||
|
||||
macro_rules! unexpected {
|
||||
($($arg:tt)*) => {
|
||||
@ -125,7 +126,7 @@ fn host_write(stream: &mut Write, reply: host::Reply) -> io::Result<()> {
|
||||
reply.write_to(stream)
|
||||
}
|
||||
|
||||
fn kern_send(io: &Io, request: &kern::Message) -> io::Result<()> {
|
||||
pub fn kern_send(io: &Io, request: &kern::Message) -> io::Result<()> {
|
||||
match request {
|
||||
&kern::LoadRequest(_) => debug!("comm->kern LoadRequest(...)"),
|
||||
&kern::DmaRetrieveReply { trace, duration } => {
|
||||
@ -176,7 +177,7 @@ fn kern_recv<R, F>(io: &Io, f: F) -> io::Result<R>
|
||||
})
|
||||
}
|
||||
|
||||
fn kern_acknowledge() -> io::Result<()> {
|
||||
pub fn kern_acknowledge() -> io::Result<()> {
|
||||
mailbox::acknowledge();
|
||||
Ok(())
|
||||
}
|
||||
@ -364,6 +365,9 @@ fn process_kern_message(io: &Io, mut stream: Option<&mut TcpStream>,
|
||||
}
|
||||
|
||||
kern_recv_dotrace(request);
|
||||
if kern_hwreq::process_kern_hwreq(io, request)? {
|
||||
return Ok(false)
|
||||
}
|
||||
match request {
|
||||
&kern::Log(args) => {
|
||||
use std::fmt::Write;
|
||||
@ -387,12 +391,6 @@ fn process_kern_message(io: &Io, mut stream: Option<&mut TcpStream>,
|
||||
kern_acknowledge()
|
||||
}
|
||||
|
||||
&kern::RtioInitRequest => {
|
||||
info!("resetting RTIO");
|
||||
rtio_mgt::init_core();
|
||||
kern_acknowledge()
|
||||
}
|
||||
|
||||
&kern::DmaRecordStart(name) => {
|
||||
session.congress.dma_manager.record_start(name);
|
||||
kern_acknowledge()
|
||||
@ -419,28 +417,6 @@ fn process_kern_message(io: &Io, mut stream: Option<&mut TcpStream>,
|
||||
})
|
||||
}
|
||||
|
||||
&kern::DrtioChannelStateRequest { channel } => {
|
||||
let (fifo_space, last_timestamp) = rtio_mgt::drtio_dbg::get_channel_state(channel);
|
||||
kern_send(io, &kern::DrtioChannelStateReply { fifo_space: fifo_space,
|
||||
last_timestamp: last_timestamp })
|
||||
}
|
||||
&kern::DrtioResetChannelStateRequest { channel } => {
|
||||
rtio_mgt::drtio_dbg::reset_channel_state(channel);
|
||||
kern_acknowledge()
|
||||
}
|
||||
&kern::DrtioGetFifoSpaceRequest { channel } => {
|
||||
rtio_mgt::drtio_dbg::get_fifo_space(channel);
|
||||
kern_acknowledge()
|
||||
}
|
||||
&kern::DrtioPacketCountRequest => {
|
||||
let (tx_cnt, rx_cnt) = rtio_mgt::drtio_dbg::get_packet_counts();
|
||||
kern_send(io, &kern::DrtioPacketCountReply { tx_cnt: tx_cnt, rx_cnt: rx_cnt })
|
||||
}
|
||||
&kern::DrtioFifoSpaceReqCountRequest => {
|
||||
let cnt = rtio_mgt::drtio_dbg::get_fifo_space_req_count();
|
||||
kern_send(io, &kern::DrtioFifoSpaceReqCountReply { cnt: cnt })
|
||||
}
|
||||
|
||||
&kern::WatchdogSetRequest { ms } => {
|
||||
let id = session.watchdog_set.set_ms(ms)
|
||||
.map_err(|()| io_error("out of watchdogs"))?;
|
||||
@ -478,44 +454,6 @@ fn process_kern_message(io: &Io, mut stream: Option<&mut TcpStream>,
|
||||
kern_send(io, &kern::CachePutReply { succeeded: succeeded })
|
||||
}
|
||||
|
||||
#[cfg(has_i2c)]
|
||||
&kern::I2cStartRequest { busno } => {
|
||||
board::i2c::start(busno);
|
||||
kern_acknowledge()
|
||||
}
|
||||
#[cfg(has_i2c)]
|
||||
&kern::I2cStopRequest { busno } => {
|
||||
board::i2c::stop(busno);
|
||||
kern_acknowledge()
|
||||
}
|
||||
#[cfg(has_i2c)]
|
||||
&kern::I2cWriteRequest { busno, data } => {
|
||||
let ack = board::i2c::write(busno, data);
|
||||
kern_send(io, &kern::I2cWriteReply { ack: ack })
|
||||
}
|
||||
#[cfg(has_i2c)]
|
||||
&kern::I2cReadRequest { busno, ack } => {
|
||||
let data = board::i2c::read(busno, ack);
|
||||
kern_send(io, &kern::I2cReadReply { data: data })
|
||||
}
|
||||
|
||||
#[cfg(not(has_i2c))]
|
||||
&kern::I2cStartRequest { .. } => {
|
||||
kern_acknowledge()
|
||||
}
|
||||
#[cfg(not(has_i2c))]
|
||||
&kern::I2cStopRequest { .. } => {
|
||||
kern_acknowledge()
|
||||
}
|
||||
#[cfg(not(has_i2c))]
|
||||
&kern::I2cWriteRequest { .. } => {
|
||||
kern_send(io, &kern::I2cWriteReply { ack: false })
|
||||
}
|
||||
#[cfg(not(has_i2c))]
|
||||
&kern::I2cReadRequest { .. } => {
|
||||
kern_send(io, &kern::I2cReadReply { data: 0xff })
|
||||
}
|
||||
|
||||
&kern::RunFinished => {
|
||||
unsafe { kernel::stop() }
|
||||
session.kernel_state = KernelState::Absent;
|
||||
|
Loading…
Reference in New Issue
Block a user