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34 Commits

Author SHA1 Message Date
Sebastien Bourdeauducq 5fd7f68f48 targets/kc705: dual-CPU design 2015-04-02 16:53:57 +08:00
Yann Sionneau e9092edb98 Remove one RTIO out channel to free up some space for travis builds to succeed 2015-03-30 19:51:52 +08:00
Florent Kermarrec 494c670cd2 targets/artiq_ppro: use new sdram_controller_settings parameter 2015-03-21 23:19:16 +01:00
Robert Jördens fdca0a71ff add ARTIQMidiSoC based on pipistrello 2015-03-19 11:37:15 -06:00
Sebastien Bourdeauducq 3122623c6f rtio: make 63-bit timestamp counter the default [soc] 2015-03-12 13:13:35 +01:00
Sebastien Bourdeauducq 28bce9ee40 artiqlib -> artiq.gateware 2015-03-08 11:00:24 +01:00
Sebastien Bourdeauducq 4e5320be28 Merge branch 'master' of https://github.com/m-labs/artiq 2015-02-28 07:34:38 -07:00
Florent Kermarrec 9cf8db2f14 adapt code to MiSoC's changes 2015-02-28 07:34:11 -07:00
Sébastien Bourdeauducq 7028d85255 targets/ppro: disable L2 2015-02-27 18:02:21 -07:00
Joe Britton 0127de9bb5 soc: add_cpu_csr_region -> add_csr_region 2015-02-27 15:02:28 -07:00
Sebastien Bourdeauducq da917f768e initial kc705 support 2015-02-26 21:50:52 -07:00
Sebastien Bourdeauducq c591f1a74d targets/ARTIQMiniSoC: support dynamic switching of RTIO clock to XTRIG 2014-12-01 18:53:29 +08:00
Sebastien Bourdeauducq 99d530e498 targets/ARTIQMiniSoC: remove 2 TTL channels to make room in FPGA 2014-12-01 17:31:35 +08:00
Sebastien Bourdeauducq 7166ca82d1 targets/ARTIQMiniSoC: map RTIO CSRs directly on Wishbone (reduces programming time by 30%) 2014-11-30 22:31:55 +08:00
Sebastien Bourdeauducq 1f6441948d more TTL channels and larger input FIFOs on Papilio Pro 2014-11-30 15:50:57 +08:00
Sebastien Bourdeauducq 39c4b5416f targets/ARTIQMiniSoC: 125MHz RTIO clocking 2014-11-30 01:00:27 +08:00
Sebastien Bourdeauducq 901073acf3 asynchronous RTIO 2014-11-30 00:13:54 +08:00
Sebastien Bourdeauducq 44ec3eae3d soc/target: use minicon by default 2014-11-28 10:21:43 +08:00
Sebastien Bourdeauducq 65567e1201 soc/target: remap RTIO to avoid conflict with Ethernet MAC+PHY 2014-11-21 15:51:51 -08:00
Sebastien Bourdeauducq 346cca9e90 soc/target: remap RTIO to avoid conflict with spiflash and ddrphy in MiSoC 2014-10-21 18:40:08 +08:00
Sebastien Bourdeauducq af0cd902d3 get frequency from RTIO, support fractional frequencies 2014-09-26 17:24:06 +08:00
Sebastien Bourdeauducq f0f65ba3a7 soc/target: add optional test signal generator 2014-09-17 19:53:55 +08:00
Sebastien Bourdeauducq 2c0b6ff4cc soc/target: connect FUD to RTIO 2014-09-11 23:11:22 +08:00
Sebastien Bourdeauducq 8d7591dfcf more PEP8 2014-09-05 17:06:41 +08:00
Sebastien Bourdeauducq 4915b4b5aa PEP8 2014-09-05 12:03:22 +08:00
Sebastien Bourdeauducq 1ed808e848 soc/target: share base PPro design with MiSoC 2014-08-03 12:26:15 +08:00
Sebastien Bourdeauducq f03ae5e5b0 soc/rtio: separate PHY, add OE and fine timestamp in FIFO 2014-07-24 23:50:20 -06:00
Robert Jördens 005d66c7cd soc/dds: fix timing 2014-07-22 17:44:41 -06:00
Sebastien Bourdeauducq 2358b218bf soc: add DDS interface core 2014-07-22 11:37:53 -06:00
Sebastien Bourdeauducq 5573cf3688 soc: add tester IO 2014-07-22 10:45:59 -06:00
Sebastien Bourdeauducq ede3667fd3 soc/target: use only 8 TTL channels for now 2014-07-20 18:38:41 -06:00
Sebastien Bourdeauducq 3b4bb41a19 add basic output-only untested RTIO core 2014-07-16 19:13:11 -06:00
Sebastien Bourdeauducq d804f1199e soc: add LED 2014-07-05 22:44:20 +02:00
Sebastien Bourdeauducq 6072f0c42f Basic SoC and runtime design 2014-07-04 17:49:08 +02:00