bdb6678cec
nix: bump migen
2019-01-31 15:13:17 +08:00
d3c608aaec
jesd204sync: reset and check lock status of DDMTD helper PLL in firmware
2019-01-31 15:11:16 +08:00
fa3b40141d
hmc830_7043: document sayma clock muxes
2019-01-31 15:10:11 +08:00
ec8560911f
siphaser: bugfixes
...
* Fix integer overflow in degree computation
* Add some phase slips after the first transition to get out of the jitter zone and avoid intermittent short windows
2019-01-30 16:56:38 +08:00
c591009220
sayma: report TSC phase of SYSREF (TSC LSBs on SYSREF rising edge) in SYSREF sampler
...
Better visibility, better diagnostics, allows some changing of SYSREF frequency while keeping the same gateware.
2019-01-29 23:30:01 +08:00
9d0d02a561
jesd204sync: increase tolerance for coarse->final target in calibrate_sysref_target
...
There is plenty of slack (it only needs to meet timing at the RTIO frequency).
2019-01-29 16:48:55 +08:00
ed6aa29897
jesd204sync: print more information on test_slip_ddmtd error
2019-01-29 16:47:29 +08:00
2e8decbce3
kasli_sawgmaster: generate a HMC830 clock with Urukul
2019-01-29 15:06:45 +08:00
9ae57fd51e
sayma: pass rtio_clk_freq to DDMTD core
2019-01-29 15:06:45 +08:00
90c9fa446f
test: add array transfer test
...
200 kB/s, more than a factor of 10 slower than the bare string transfer
Signed-off-by: Robert Jördens <rj@quartiq.de>
2019-01-28 14:30:44 +00:00
7a5d28b73d
jesd204sync: test SYSREF period
2019-01-28 19:11:38 +08:00
1a42e23fb4
jesd204sync: print DDMTD SYSREF final alignment delta
2019-01-28 18:39:16 +08:00
eebff6d77f
jesd204sync: fix max_phase_deviation
2019-01-28 18:38:18 +08:00
b9e3fab49c
jesd204sync: improve messaging
2019-01-28 18:37:46 +08:00
145f08f3fe
jesd204sync: update SYSREF S/H limit deviation tolerance
...
Follows the increased DDMTD resolution.
2019-01-28 18:21:31 +08:00
ba21dc8498
jesd204sync: improve messaging
2019-01-28 18:08:20 +08:00
3acee87df2
firmware: improve DDMTD resolution using dithering/averaging
2019-01-28 16:04:04 +08:00
cfe66549ff
jesd204sync: cleanup DDMTD averaging code
2019-01-28 14:14:50 +08:00
2b0d63db23
hmc830_7043: support 125MHz RTIO
2019-01-28 13:44:08 +08:00
bdd4e52a53
ad9154: support 125MHz RTIO
2019-01-28 13:43:52 +08:00
47312e55d3
sayma: set RTIO_FREQUENCY in MasterDAC
2019-01-28 13:43:28 +08:00
443d6d8688
sayma_amc: pass RTIO clock frequency to SiPhaser
2019-01-28 09:49:03 +08:00
3b6f47886e
firmware: print more info on DDMTD stability error
2019-01-27 23:06:11 +08:00
74fdd04622
firmware: test DDMTD stability
2019-01-27 20:39:12 +08:00
81b0046f98
ddmtd: add deglitchers
2019-01-27 20:38:41 +08:00
8254560577
sayma: properly determine SYSREF coarse calibration target
2019-01-27 16:00:36 +08:00
214394e3b0
sayma: reimplement DAC SYSREF autocalibration
2019-01-27 15:28:39 +08:00
fdbf1cc2b2
sayma: rework DAC SYSREF margin validation
...
Previous code did not work when delay range was not enough for two rotations.
This removes autocalibration, to be done later. Uses hardcoded value for now.
2019-01-27 14:17:54 +08:00
7e5c062c2c
firmware: bypass channel divider for HMC7043 DCLK
2019-01-27 11:49:34 +08:00
f73ffe44f9
firmware: implement DDMTD-based SYSREF/RTIO alignment (draft)
...
Mostly works and usually gets the DAC synchronized at 2.4GHz with Urukul across DRTIO.
Needs cleanup and optimization/characterization.
2019-01-27 09:51:24 +08:00
8632b553d2
ddmtd: use IOB register to sample input
2019-01-27 09:50:02 +08:00
d1ef036948
kasli_sawgmaster: initialize SAWG phase according to RTIO TSC
2019-01-27 09:49:31 +08:00
9966e789fc
sayma: simplify Ultrascale LVDS T false path
...
Recommended by Xilinx.
2019-01-25 23:40:48 +08:00
359fb1f207
sayma: fix DDMTD STA
2019-01-25 23:39:19 +08:00
cb04230f86
sayma: SYSREF setup/hold validation demonstration
...
This also removes the standalone target as the ISERDES used
for setup/hold check requires the fine RTIO clock, which in turn
requires a DRTIO transceiver due to the Ultrascale TPWS bug.
2019-01-25 16:58:58 +08:00
3356717316
sayma: DDMTD SYSREF measurement demonstration
2019-01-25 16:00:31 +08:00
4941fb3300
sayma: 2.4GHz DAC clocking (4X interpolation)
...
* gets another clock divider out of the way
* gets one cycle within range of the HMC7043 analog delay alone
* SYSREF/RTIO alignment removed, to be replaced with DDMTD-based scheme
2019-01-25 13:47:04 +08:00
cc9420d2c8
hmc7043: fix divider programming
2019-01-25 11:48:50 +08:00
8c5a502591
ad53xx: ignore F3 (reserved)
...
Signed-off-by: Robert Jördens <rj@quartiq.de>
2019-01-24 15:50:46 +01:00
bbac92442f
sayma: check hmc7043 slip period
2019-01-24 20:13:43 +08:00
a92cc91dcb
kasli_sawgmaster: correctly tune DDS and SAWG
2019-01-24 19:37:14 +08:00
f8b39b0b9a
sayma: enable 2X DAC interpolation
...
Seems to work just fine and gets one clock divider out of the way.
2019-01-24 18:28:01 +08:00
07b5b0d36d
kasli: adapt Master target to new hardware
2019-01-24 18:27:15 +08:00
31592fc8e4
nix: install flash proxy bitstreams with OpenOCD
2019-01-24 16:47:37 +08:00
0a0e8c3c93
nix: bump migen/misoc
2019-01-24 16:20:02 +08:00
3917a0ef46
nix: support reusing dev environment in build scripts
2019-01-23 21:59:39 +08:00
154269b77a
kasli: fix HUST satellite Urukul
2019-01-23 17:59:43 +08:00
3b5fd3ac11
kasli_tester: fix grabber test
2019-01-23 17:59:25 +08:00
330c5610e9
ad9912: fix imports
2019-01-23 17:59:08 +08:00
390f05f762
firmware: use smoltcp release
2019-01-23 16:15:05 +08:00
