forked from M-Labs/artiq
1
0
Fork 0
Commit Graph

5962 Commits

Author SHA1 Message Date
Robert Jördens 3a0dfb7fdc ad53xx: port monitor, moninj dashboard, kc705 target 2018-03-24 16:04:02 +01:00
Robert Jördens a8f0ee1c86 ad53xx: refactor offset_to_mu(), fix docs 2018-03-24 15:45:42 +01:00
Robert Jördens b0c8097025 ad53xx: remove channel index AND
It's incorrect since it doesn't respect the number of channels
of any of those chips (none has 64 channels).
2018-03-24 15:39:06 +01:00
Robert Jördens 77bcc2c78f zotino: style, use attributes to set SPI config 2018-03-24 15:37:34 +01:00
Robert Jördens 22557294ac RELEASE_NOTES: ad53xx, zotino 2018-03-24 15:20:04 +01:00
Robert Jördens 9bc2ce84fc doc: ad5360 -> ad53xx, add zotino 2018-03-24 15:18:08 +01:00
Robert Jördens 2cf414a480 ad53xx: move 8 bit shift out of ad53xx protocol funcs
That's specific to the SPI bus, not to the ad53xx.
2018-03-24 15:15:56 +01:00
Robert Jördens 08326c5727 ad53xx: style [nfc] 2018-03-24 14:10:20 +01:00
Robert Jördens 68e433a3a8 opticlock/device_db: resurrect novogorny
deleted in a992a67
2018-03-24 13:46:45 +01:00
hartytp a992a672d9 coredevice/zotino: add (#969)
* Replace ad5360 driver with a ad53xx driver, designed to have a nicer interface
Add Zotino driver and add to opticlock target for Kasli
Test Zotino on hw:
 - Verify all timings on the hardware with a scope
 - Verify that we can correctly set and read back all registers in a loop (checks for SI and driver issues)
 - check we can set LEDs correctly
 - check calibration routine + all si unit functions with a good DVM
 - look at DAC transitions on a scope (while triggering of a TTL) on persist to check there are no LDAC glitches etc
To do: update examples and e.g. KC705 device db.
2018-03-24 13:41:18 +01:00
Robert Jördens 1553fc8c7d sed: reset `valid` in output sorter 2018-03-23 11:11:11 +00:00
Sebastien Bourdeauducq 0635907699 artiq_flash: fix cmdline formatting 2018-03-22 19:10:29 +08:00
Sebastien Bourdeauducq 46d5af31a1 artiq_flash: enclose filename in curly braces before passing to OpenOCD
Closes #927
2018-03-22 17:20:48 +08:00
Sebastien Bourdeauducq eeedcfbdd7 artiq_flash: do not suppress useful backtrace information 2018-03-22 17:11:21 +08:00
Sebastien Bourdeauducq f2cc2a5ff2 firmware: reset local RTIO PHYs on startup (#958) 2018-03-22 16:29:31 +08:00
Sebastien Bourdeauducq 40e2ced85e manual: fix core_drivers_reference 2018-03-22 13:26:45 +08:00
Sebastien Bourdeauducq 9eb0218389 RELEASE_NOTES: add sections for major releases 2018-03-22 13:26:28 +08:00
Sebastien Bourdeauducq 102e3983b5 manual: reorganize core drivers 2018-03-22 12:06:01 +08:00
Sebastien Bourdeauducq 1b91339865 manual: fix text role 2018-03-22 12:05:47 +08:00
Sebastien Bourdeauducq 06f24c6aa2 RELEASE_NOTES: update 2018-03-22 11:46:41 +08:00
Robert Jördens 770b0a7b79 novogorny: conv -> cnv
* parity with sampler
* also add novogorny device to opticlock
2018-03-21 18:38:42 +00:00
Robert Jördens 82c4f0eed4 sampler: fix channel gain retrieval 2018-03-21 14:22:13 +01:00
Robert Jördens 12d699f2a8 suservo: add sampler example 2018-03-21 12:21:53 +00:00
Robert Jördens 97918447a3 sampler: add coredevice driver 2018-03-21 12:21:53 +00:00
Robert Jördens 1afce8c613 kasli: simplify single eem pin formatting 2018-03-21 13:08:42 +01:00
Robert Jördens d48b8f3086 kasli: fix sampler sdr/cnv pins 2018-03-21 09:28:00 +00:00
Robert Jördens 80903cead7 novogorny: streamline gain setting method, style [nfc] 2018-03-21 08:53:26 +00:00
Robert Jördens f5a1001114 suservo: add device database and artiq_flash variant 2018-03-21 08:53:26 +00:00
Robert Jördens 1fb5907362 kasli: add SUServo variant (Sampler-Urukul Servo) 2018-03-21 08:53:26 +00:00
Robert Jördens f74d5772f4 sampler: add wide eem definition 2018-03-21 08:53:26 +00:00
Sebastien Bourdeauducq 32f22f4c9c sayma: disable SERDES TTL entirely
Timing closure becomes very random, even at 4X.
2018-03-21 13:03:48 +08:00
Sebastien Bourdeauducq f8c2d54e75 ttl_serdes_ultrascale: configurable SERDES ratio. Also try X4 on Sayma 2018-03-21 13:01:38 +08:00
Sebastien Bourdeauducq 9c2d343052 sayma: use SERDES RTIO TTL
This is not enabled on the standalone design as it breaks timing.
2018-03-21 10:53:52 +08:00
Robert Jördens 9ad1fd8f25 urukul: add comment and doc about the AD9910 MASTER_RESET 2018-03-20 17:40:03 +01:00
Robert Jördens f17c0abfe4 urukul: don't pulse DDS_RST on init
closes m-labs/artiq#940

Apparently, if the DDS are reset, every other time they don't work
properly.
2018-03-20 16:10:26 +00:00
Robert Jördens a185e8dc52 urukul: fix MASK_NU offset 2018-03-20 16:10:11 +00:00
Robert Jördens f4719ae24b sdram: clean up console output 2018-03-20 15:42:49 +01:00
Robert Jördens 206664afd9 sdram: compact read_level output 2018-03-20 10:16:05 +00:00
Robert Jördens 495625b99d bootloader: repeat memory test 4 times 2018-03-20 09:57:49 +00:00
Robert Jördens 6fb0cbfcd3 sdram: clean up, make read_level robust to wrap around
* fix a few rust warnings
* also do eye scans on kintex
2018-03-20 09:57:49 +00:00
Robert Jördens 3abb378fbe i2c: unused variable 2018-03-20 09:56:26 +00:00
Sebastien Bourdeauducq c8020f6bbd ttl_serdes_generic: fix/upgrade test 2018-03-20 16:46:57 +08:00
Sebastien Bourdeauducq a5825184b7 add ttl_serdes_ultrascale (untested) 2018-03-20 16:07:23 +08:00
Sebastien Bourdeauducq fad066f1aa ttl_serdes_7series: cleanup indentation
Inconsistent with other code and confuses text editors.
2018-03-20 15:50:04 +08:00
Robert Jördens 276b0c7f06 sdram: reject read delay wrap arounds 2018-03-20 00:28:41 +01:00
Robert Jördens 65379b1f7a conda: bump migen, misoc
* xilinx ODDR2 SRTYPE
* flterm leak
* I/ODELAY VTC/reset sequencing
* sayma SDRAM clock buffer LOC
2018-03-19 19:58:52 +01:00
Robert Jördens 4b3f408143 sdram: simplify read level scan 2018-03-19 18:41:56 +00:00
Robert Jördens 845784c180 kusddrphy: use first and last tap that yield many valid reads 2018-03-19 17:54:26 +00:00
Robert Jördens ed2e0c8b34 sayma/sdram/scan: test each tap 1024 times 2018-03-20 00:59:31 +08:00
hartytp a27b5d88c2 Novogorny driver, remove unused imports (#964)
* Novogorny driver, remove unused imports

* more unused imports

* oops, one final one!
2018-03-19 11:58:14 +01:00