forked from M-Labs/artiq
sampler: add coredevice driver
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from artiq.language.core import kernel, delay, portable
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from artiq.language.units import ns
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from artiq.coredevice import spi2 as spi
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SPI_CONFIG = (0*spi.SPI_OFFLINE | 0*spi.SPI_END |
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0*spi.SPI_INPUT | 0*spi.SPI_CS_POLARITY |
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0*spi.SPI_CLK_POLARITY | 0*spi.SPI_CLK_PHASE |
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0*spi.SPI_LSB_FIRST | 0*spi.SPI_HALF_DUPLEX)
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SPI_CS_ADC = 0 # no CS, SPI_END does not matter, framing is done with CNV
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SPI_CS_PGIA = 1 # separate SPI bus, CS used as RCLK
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@portable
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def adc_mu_to_volt(data, gain=0, v_ref=5.):
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"""Convert ADC data in machine units to Volts.
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:param data: 16 bit signed ADC word
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:param gain: PGIA gain setting (0: 1, ..., 3: 1000)
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:param v_ref: Reference voltage in Volts
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:return: Voltage in Volts
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"""
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for i in range(gain):
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v_ref /= 10.
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volt_per_lsb = v_ref/(1 << 15)
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return data*volt_per_lsb
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class Sampler:
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"""Sampler ADC.
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Controls the LTC2320-16 8 channel 16 bit ADC with SPI interface and
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the switchable gain instrumentation amplifiers.
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:param spi_adc_device: ADC SPI bus device name
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:param spi_pgia_device: PGIA SPI bus device name
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:param cnv_device: CNV RTIO TTLOut channel name
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:param div: SPI clock divider (default: 8)
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:param core_device: Core device name
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"""
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kernel_invariants = {"bus_adc", "bus_pgia", "core", "cnv", "div", "v_ref"}
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def __init__(self, dmgr, spi_adc_device, spi_pgia_device, cnv_device,
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div=8, core_device="core"):
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self.bus_adc = dmgr.get(spi_adc_device)
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self.bus_pgia = dmgr.get(spi_pgia_device)
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self.core = dmgr.get(core_device)
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self.cnv = dmgr.get(cnv_device)
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self.div = div
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self.gains = 0x0000
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self.v_ref = 10. # 5 Volt reference, 0.5 AFE diff gain
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@kernel
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def init(self):
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"""Initialize the device.
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Sets up SPI channels.
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"""
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self.bus_adc.set_config_mu(SPI_CONFIG | spi.SPI_INPUT | spi.SPI_END,
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32, self.div, SPI_CS_ADC)
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self.bus_pgia.set_config_mu(SPI_CONFIG | spi.SPI_END,
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16, self.div, SPI_CS_PGIA)
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@kernel
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def set_gain_mu(self, channel, gain):
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"""Set instrumentation amplifier gain of a channel.
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The four gain settings (0, 1, 2, 3) corresponds to gains of
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(1, 10, 100, 1000) respectively.
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:param channel: Channel index
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:param gain: Gain setting
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"""
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gains = self.gains
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gains &= ~(0b11 << (channel*2))
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gains |= gain << (channel*2)
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self.bus_pgia.write(gains << 16)
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self.gains = gains
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@kernel
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def get_gains_mu(self):
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"""Read the PGIA gain settings of all channels.
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:return: The PGIA gain settings in machine units.
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"""
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self.bus_pgia.set_config_mu(SPI_CONFIG | spi.SPI_END | spi.SPI_INPUT,
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16, self.div, SPI_CS_PGIA)
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self.bus_pgia.write(self.gains << 16)
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self.bus_pgia.set_config_mu(SPI_CONFIG | spi.SPI_END,
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16, self.div, SPI_CS_PGIA)
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self.gains = self.bus_pgia.read() & 0xffff
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return self.gains
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@kernel
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def sample_mu(self, data):
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"""Acquire a set of samples.
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Perform a conversion and transfer the samples.
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This assumes that the input FIFO of the ADC SPI RTIO channel is deep
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enough to buffer the samples (half the length of `data` deep).
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If it is not, there will be RTIO input overflows.
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:param data: List of data samples to fill. Must have even length.
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Samples are always read from the last channel (channel 7) down.
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The `data` list will always be filled with the last item
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holding to the sample from channel 7.
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"""
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self.cnv.pulse(30*ns) # t_CNVH
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delay(450*ns) # t_CONV
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mask = 1 << 15
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for i in range(len(data)//2):
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self.bus_adc.write(0)
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for i in range(len(data) - 1, -1, -2):
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val = self.bus_adc.read()
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data[i] = val >> 16
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val &= 0xffff
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data[i - 1] = -(val & mask) + (val & ~mask)
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@kernel
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def sample(self, data):
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"""Acquire a set of samples.
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.. seealso:: :meth:`sample_mu`
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:param data: List of floating point data samples to fill.
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"""
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n = len(data)
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adc_data = [0]*n
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self.sample_mu(adc_data)
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for i in range(n):
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channel = 8 - len(data)
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gain = (self.gains >> (channel*2)) & 0b11
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data[i] = adc_mu_to_volt(adc_data[i], gain, self.v_ref)
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@ -81,6 +81,12 @@ These drivers are for the core device and the peripherals closely integrated int
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.. automodule:: artiq.coredevice.novogorny
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:members:
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:mod:`artiq.coredevice.sampler` module
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--------------------------------------
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.. automodule:: artiq.coredevice.sampler
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:members:
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:mod:`artiq.coredevice.urukul` module
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-------------------------------------
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