forked from M-Labs/artiq
urukul: add comment and doc about the AD9910 MASTER_RESET
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@ -166,9 +166,12 @@ class CPLD:
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def init(self):
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"""Initialize and detect Urukul.
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Resets the DDS and verifies correct CPLD gateware version.
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Resets the DDS I/O interface and verifies correct CPLD gateware
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version.
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Does not pulse the DDS MASTER_RESET as that confuses the AD9910.
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"""
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cfg = self.cfg_reg
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# Don't pulse MASTER_RESET (m-labs/artiq#940)
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self.cfg_reg = cfg | (0 << CFG_RST) | (1 << CFG_IO_RST)
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proto_rev = urukul_sta_proto_rev(self.sta_read())
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if proto_rev != STA_PROTO_REV_MATCH:
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